ReVAMP: ReRAM based VLIW architecture for in-memory computing

Bhattacharjee, Debjyoti; Devadoss, Rajeswari; Chattopadhyay, Anupam

doi:10.23919/date.2017.7927095

Cited by 58 publications

(24 citation statements)

References 14 publications

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“…PLiM implemented only serial operation to keep the controller as simple as possible. In Reference [15] the authors presented ReVAMP, an architecture composed of two ReRAM crossbars, supporting parallel computations and VLIW-like instructions. To perform logic operations ReVAMP exploits the native properties of ReRAM cells that implement a majority voting logic function.…”

Section: Reram-basedmentioning

confidence: 99%

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

Turvani

Santoro

et al. 2020

Sensors

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To live in the information society means to be surrounded by billions of electronic devices full of sensors that constantly acquire data. This enormous amount of data must be processed and classified. A solution commonly adopted is to send these data to server farms to be remotely elaborated. The drawback is a huge battery drain due to high amount of information that must be exchanged. To compensate this problem data must be processed locally, near the sensor itself. But this solution requires huge computational capabilities. While microprocessors, even mobile ones, nowadays have enough computational power, their performance are severely limited by the Memory Wall problem. Memories are too slow, so microprocessors cannot fetch enough data from them, greatly limiting their performance. A solution is the Processing-In-Memory (PIM) approach. New memories are designed that can elaborate data inside them eliminating the Memory Wall problem. In this work we present an example of such a system, using as a case of study the Bitmap Indexing algorithm. Such algorithm is used to classify data coming from many sources in parallel. We propose a hardware accelerator designed around the Processing-In-Memory approach, that is capable of implementing this algorithm and that can also be reconfigured to do other tasks or to work as standard memory. The architecture has been synthesized using CMOS technology. The results that we have obtained highlights that, not only it is possible to process and classify huge amount of data locally, but also that it is possible to obtain this result with a very low power consumption.in slow accesses compared to processors computing speed. This discrepancy in performance harms the computing abilities of the CPU, since the memory cannot provide data as quickly as required by the CPU. This problem is called Von Neumann bottleneck or Memory Wall. The idea that took form to solve this problem is to null the distance between processor and memory, removing the cost of data transfer and create a unit which is capable of storing information and of performing operation on them. This idea takes the name of Processing-in-Memory.Many in literature have approached the "in-memory" idea. Some narrowing the physical distance between memory and computation unit by creating and stacking different layers together. But even if the two units are moved very close to each other, they are still distinct components. Others exploited intrinsic functionality of the memory array or slightly modified peripheral circuitry to perform computation.Among the many example provided by literature, one of the best fitting representative of the PIM concept is presented in Reference [1]. In this work the proposed architecture is a memory array in which the cell itself is capable of performing logical operations aimed at solving Convolutional Neural Networks (CNN). In this paper, our main goal is to introduce a proper example of Processing-in-Memory, choosing Bitmap Indexing as an application around which the architecture is shaped. In th...

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Section: Reram-basedmentioning

confidence: 99%

Data Processing and Information Classification—An In-Memory Approach

Andrighetti

Turvani

Santoro

et al. 2020

Sensors

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“…• CIM-Array (CIM-A): In CIM-A, the computation result is produced within the array. Examples of such architectures are PLiM [23], ReVAMP [24], CIM device [25], etc. The CIM-A core typically requires a significant redesign of the memory array to support computing, as conventional memory cell layouts are typically optimized for storage functionality only.…”

Section: A Cim Concept and Classificationmentioning

confidence: 99%

Testing Computation-in-Memory Architectures Based on Emerging Memories

Hamdioui

Fieback

Nagarajan

et al. 2019

2019 IEEE International Test Conference (ITC)

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Today's computing architectures and device technologies are becoming incapable of meeting the increasingly stringent demands on energy and performance posed by evolving applications. Therefore, alternative novel post-CMOS computing architectures are being explored. Some of these are Computationin-Memory (CIM) architectures based on memristive devices; they integrate the processing units and the storage in the same physical location (i.e., the memory based on memristive devices). Due to their advanced manufacturing processes, use of new materials, and dual functionality, testing such chips requires specific schemes and therefore special attention. This paper describes the need for testing CIM architectures, proposes a systematic test approach, and shows the strong dependency of the test solutions on the nature of the architecture. All of these will be demonstrated using a design that is designed for computationin-memory bit-wise logical operations.

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“…Inherently, ReRAM arrays support operations arXiv:1809.08195v1 [cs.ET] 21 Sep 2018 on multiple devices that are on the same wordline, allowing parallel operations. The ReVAMP architecture allows harnessing this parallelism by means of VLIW instructions [36].…”

Section: Introductionmentioning

confidence: 99%

Crossbar-Constrained Technology Mapping for ReRAM Based In-Memory Computing

Bhattacharjee

Tavva

Easwaran

et al. 2020

IEEE Trans. Comput.

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In recent times, Resistive RAMs (ReRAMs) have gained significant prominence due to their unique feature of supporting both non-volatile storage and logic capabilities. ReRAM is also reported to provide extremely low power consumption compared to the standard CMOS storage devices. As a result, researchers have explored the mapping and design of diverse applications, ranging from arithmetic to neuromorphic computing structures to ReRAM-based platforms. ReVAMP, a generalpurpose ReRAM computing platform, has been proposed recently to leverage the parallelism exhibited in a crossbar structure. However, the technology mapping on ReVAMP remains an open challenge. Though the technology mapping with device/areaconstraints have been proposed, crossbar constraints are not considered so far. In this work, we address this problem. Two technology mapping flows are proposed, considering different runtime-efficiency trade-offs. Both the mapping flows take crossbar constraints into account and generate feasible mapping for a variety of crossbar dimensions. Our proposed algorithms are highly scalable and reveal important design hints for ReRAMbased implementations.

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ReVAMP: ReRAM based VLIW architecture for in-memory computing

Cited by 58 publications

References 14 publications

Data Processing and Information Classification—An In-Memory Approach

Data Processing and Information Classification—An In-Memory Approach

Testing Computation-in-Memory Architectures Based on Emerging Memories

Crossbar-Constrained Technology Mapping for ReRAM Based In-Memory Computing

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