Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture

Abstract

A reusable, low-cost, and flexible multidrop system JTAG' architecture has been developed at Brocade as an alternative to more expensive commercial solutions. This architecture allows JTAG operations to be driven by a local on-board processor or an external host. An adddrop network design allows all on-board JTAG devices to be grouped into several smaller chains and enables the chains to be combined flexibly for various JTAG operations. By implementing this architecture in a lowcost Complex Programmable Logic Device (CPLD), it has been used in stand-alone single-board systems as well as complex multiboard chassis systems at Brocade.

Design and Implementation of Repair-aware Test Flow for Multi-Memory

“…The BIRA circuit receives the detected faulty information and stores the information, after analysis it according to the RA ( Redundancy Analysis ) algorithm, allocates redundancies. The control part communicates with outside control signal by the JATG ports [11]. The most striking parts of the circuit are distributed BISTs and a shared BIRA, which will be discussed below.…”