Rethinking DRAM's Page Mode With STT-MRAM

Oh, Byoungchan; Abeyratne, Nilmini; Kim, Nam Sung; Ahn, Jeongseob; Dreslinski, Ronald G.; Mudge, Trevor

doi:10.1109/tc.2022.3207131

Cited by 1 publication

(6 citation statements)

References 36 publications

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“…Another issue with STT-MRAM is its modified sensing methods. The SMART system in [23], uses a modified approach for STT-MRAM to address the sensing challenges more efficiently than DRAM. SMART's sense amplifier design reduces row buffer size, leading to higher activation energy and lower performance.…”

Section: Related Workmentioning

confidence: 99%

“…In the absence of reliable current and timing parameters from manufacturers, the proposed SOT-MRAM-based main memory for the multicore environment uses approaches demonstrated in [1], [10], [23]. These methods use simulators and commercially available hardware to validate their timing and current parameter scaling methodology.…”

Section: Sot-mram Main Memorymentioning

confidence: 99%

“…The evaluation involves deriving and using separate scaled parameters for row bufferassociated and non-associated parameters. We estimated and scaled the timing and power parameters using established and validated methods outlined in previous studies such as [1] and [23]. Additionally, we conducted circuit-level memory exploration experiments to further validate the scaling factors employed.…”

Section: Sot-mram Main Memorymentioning

confidence: 99%

“…In this study, a conservative scaling of SOT-MRAM parameters from DRAM-1600 is adopted using the methodology in [1], [34]. The scaling methodology was validated in the work [1] and [23]. SOT-MRAM tRFC(Refresh cycle time) and tRAS(Activate to precharge delay) values are taken as 0.…”

Section: A Parameters For Estimation Of Timingmentioning

confidence: 99%

“…SOT-MRAM uses current mode to access its cells, in comparison to DRAM's voltage-mode cell operations. So we choose the same methodology adopted in timing parameter estimation and scale the values to account for current-based sensing methods of SOT-MRAM as in [1], [23]. In the case of SOT-MRAM, since it does not require refresh, the Refresh Current (IDD5) and Self Refresh Current (IDD6) are set to 0.…”

Section: B Parameters For Estimation Of Powermentioning

confidence: 99%

See 4 more Smart Citations

A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment

Kallinatha,

Rai,

Talawar

2024

IEEE Access

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Alternative memory technologies must be explored to foster the need for modern applications. This work proposes a novel approach incorporating Spin-Orbit-Torque-Magnetic-RAM (SOT-MRAM) into hybrid and full main memory architectures within a multi-core system, encompassing various memory configurations and capacities. The study addresses the challenge of evaluating SOT-MRAM-based memory systems when specific SOT-MRAM memory parameters are not publicly available. The research methodology encompasses micro-architectural (circuit-level) design space exploration and comprehensive full system simulations, which evaluate benchmark programs representing diverse application domains. The evaluation includes three memory structures with varying memory organizations and capacities. The results underscore SOT-MRAM as a robust replacement for DRAM or hybrid memory, offering compelling advantages such as a remarkable 74.05% reduction in power consumption, a noteworthy 40.10% increase in bandwidth utilization, and a significant 72.85% reduction in Energy-Delay Product (EDP). Additionally, the incurred maximum latency penalties are minimal, with a 3.71% increase for hybrid structures and a mere 0.07% for standalone SOT-MRAM memory structures.

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Section: Related Workmentioning

confidence: 99%