Rethinking DRAM Power Modes for Energy Proportionality

Malladi, Krishna T.; Shaeffer, Ian; Gopalakrishnan, Liji; Lo, David; Lee, Benjamin C.; Horowitz, Mark

doi:10.1109/micro.2012.21

Cited by 62 publications

(32 citation statements)

References 35 publications

(43 reference statements)

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“…We used these techniques to build zsim, a validated simulator that reaches speeds up to 1,500 MIPS on thousand-core simulations and supports a wide range of workloads. ZSim is currently used by several research groups, has been used in multiple publications [36,37,38,39,23,24], and is publicly available under a free software license.…”

Section: Discussionmentioning

confidence: 99%

ZSim

Sánchez

Kozyrakis

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

314

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Architectural simulation is time-consuming, and the trend towards hundreds of cores is making sequential simulation even slower. Existing parallel simulation techniques either scale poorly due to excessive synchronization, or sacrifice accuracy by allowing event reordering and using simplistic contention models. As a result, most researchers use sequential simulators and model small-scale systems with 16-32 cores. With 100-core chips already available, developing simulators that scale to thousands of cores is crucial.We present three novel techniques that, together, make thousand-core simulation practical. First, we speed up detailed core models (including OOO cores) with instructiondriven timing models that leverage dynamic binary translation. Second, we introduce bound-weave, a two-phase parallelization technique that scales parallel simulation on multicore hosts efficiently with minimal loss of accuracy. Third, we implement lightweight user-level virtualization to support complex workloads, including multiprogrammed, client-server, and managed-runtime applications, without the need for full-system simulation, sidestepping the lack of scalable OSs and ISAs that support thousands of cores.We use these techniques to build zsim, a fast, scalable, and accurate simulator. On a 16-core host, zsim models a 1024-core chip at speeds of up to 1,500 MIPS using simple cores and up to 300 MIPS using detailed OOO cores, 2-3 orders of magnitude faster than existing parallel simulators. Simulator performance scales well with both the number of modeled cores and the number of host cores. We validate zsim against a real Westmere system on a wide variety of workloads, and find performance and microarchitectural events to be within a narrow range of the real system.

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Section: Discussionmentioning

confidence: 99%

ZSim

Sánchez

Kozyrakis

2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

314

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“…Several previous studies deal with the energy efficiency of DRAM memory, through different memory management policies, intelligent data placement, and by creating opportunities to transition between power states [9,16,24]. Malladi et al [15] use mobile DRAM devices in order to trade bandwidth for energy efficiency.…”

Section: Related Workmentioning

confidence: 99%

Large-Memory Nodes for Energy Efficient High-Performance Computing

Zivanovic

Radulovic

Llort

et al. 2016

Proceedings of the Second International Symposium on Memory Systems

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Energy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have received significant research and development effort, but a simple measure that can dramatically reduce energy consumption is often overlooked. We show that, in capacity computing, where many small to medium-sized jobs have to be solved at the lowest cost, a practical energy-saving approach is to scale-in the application on large-memory nodes. We evaluate scaling-in; i.e. decreasing the number of application processes and compute nodes (servers) to solve a fixedsized problem, using a set of HPC applications running in a production system. Using standard-memory nodes, we obtain average energy savings of 36%, already a huge figure. We show that the main source of these energy savings is a decrease in the node-hours (node hours = #nodes × exe time), which is a consequence of the more efficient use of hardware resources.Scaling-in is limited by the per-node memory capacity. We therefore consider using large-memory nodes to enable a greater degree of scaling-in. We show that the additional energy savings, of up to 52%, mean that in many cases the investment in upgrading the hardware would be recovered in a typical system lifetime of less than five years.

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“…In addition, the Obj-Store also captures the locality within an iteration and filters small width (4-byte) accesses from the LLC to save energy. Obj-Store is organized as a fully associative decoupled sector-cache [34] with a sector size of 4 bytes (8 sectors/line) [24] and 32 tag entries ( Figure 4). The decoupled sector organization provides the following benefits : i) by varying the number of sectors allocated data objects of varying length are supported ii) the small sector sizes (4 bytes) support structures of primitive type (e.g., array of floats), iii) tag overhead is minimized.…”

Section: Obj-storementioning

confidence: 99%

Dasx

Kumar

Vedula

Shriraman

et al. 2015

Proceedings of the 29th ACM on International Conference on Supercomputing

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Recent research [3,37,38] has proposed compute accelerators to address the energy efficiency challenge. While these compute accelerators specialize and improve the compute efficiency, they have tended to rely on address-based load/store memory interfaces that closely resemble a traditional processor core. The address-based load-/store interface is particularly challenging in data-centric applications that tend to access different software data structures. While accelerators optimize the compute section, the address-based interface leads to wasteful instructions and low memory level parallelism (MLP). We study the benefits of raising the abstraction of the memory interface to data structures.We propose DASX (Data Structure Accelerator), a specialized state machine for data fetch that enables compute accelerators to efficiently access data structure elements in iterative program regions. DASX enables the compute accelerators to employ data structure based memory operations and relieves the compute unit from having to generate addresses for each individual object. DASX exploits knowledge of the program's iteration to i) run ahead of the compute units and gather data objects for the compute unit (i.e., compute unit memory operations do not encounter cache misses) and ii) throttle the fetch rate, adaptively tile the dataset based on the locality characteristics and guarantee cache residency. We demonstrate accelerators for three types of data structures, Vector, Key-Value (Hash) maps, and BTrees. We demonstrate the benefits of DASX on data-centric applications which have varied compute kernels but access few regular data structures. DASX achieves higher energy efficiency by eliminating data structure instructions and enabling energy efficient compute accelerators to efficiently access the data elements. We demonstrate that DASX can achieve 4.4⇥ the performance of a multicore system by discovering more parallelism from the data structure.

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Rethinking DRAM Power Modes for Energy Proportionality

Cited by 62 publications

References 35 publications

ZSim

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Large-Memory Nodes for Energy Efficient High-Performance Computing

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