Rethinking Digital Design: Why Design Must Change

Shacham, Ofer; Azizi, Omid; Wachs, Megan; Qadeer, Wajahat; Asgar, Zain; Kelley, Kyle; Stevenson, John P.; Richardson, Stephen; Horowitz, Mark; Lee, Benjamin; Solomatnikov, Alex; Firoozshahian, Amin

doi:10.1109/mm.2010.81

Cited by 71 publications

(26 citation statements)

References 16 publications

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“…Our parser generator is built using the Genesis [14] chip generator. Genesis is a tool that generates design instances using an architectural "template" and a set of application configuration parameters.…”

Section: Parser Generatormentioning

confidence: 99%

Design principles for packet parsers

Gibb

Varghese

Horowitz

et al. 2013

Architectures for Networking and Communications Systems

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All network devices must parse packet headers to decide how packets should be processed. A 64 × 10 Gb/s Ethernet switch must parse one billion packets per second to extract fields used in forwarding decisions. Although a necessary part of all switch hardware, very little has been written on parser design and the trade-offs between different designs. Is it better to design one fast parser, or several slow parsers? What is the cost of making the parser reconfigurable in the field? What design decisions most impact power and area?In this paper, we describe trade-offs in parser design, identify design principles for switch and router designers, and describe a parser generator that outputs synthesizable Verilog that is available for download. We show that i) packet parsers today occupy about 1-2% of the chip, and ii) while future packet parsers will need to be programmable, this only doubles the (already small) area needed.

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Section: Parser Generatormentioning

confidence: 99%

Design principles for packet parsers

Gibb

Varghese

Horowitz

et al. 2013

Architectures for Networking and Communications Systems

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“…We argue that the specialized engine approach does not avoid two significant pitfalls of ASICs: hardware verification costs and excessive software specialization. According to [3,33], the main cost factors in hardware development are design/verification (∼40%) followed by developing the companion software (∼30%). Designing lookup engines still requires complex and costly hardware/software codesign; lookup algorithms developed for a platform are highly specialized and cannot be ported to different architectures.…”

Section: Network Lookupsmentioning

confidence: 99%

“…In addition, SWSL requires no profiler because it generates hardware logic for the whole lookup pipeline. In other words, SWSL can be considered as a SWSL chip generator of lookup engines [33].…”

Section: Hlsmentioning

confidence: 99%

“…However, as providing both complete programmability and performance is an impractical goal, these specialized approaches still have to prioritize one or the other. Moreover, recent industry trends [3,33] show that the main cost factors in hardware development are design/verification, followed by developing the companion software. Specialized engines still incur design/verification costs, although amortized.…”

Section: Introductionmentioning

confidence: 99%

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SWSL: SoftWare Synthesis for network Lookup

Kim¹,

Carli²,

Sankaralingam³

et al. 2013

Architectures for Networking and Communications Systems

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Data structure lookups are among the most expensive operations on routers' critical path in terms of latency and power. Therefore, efficient lookup engines are crucial. Several approaches have been proposed, based on either custom ASICs, general-purpose processors, or specialized engines. ASICs enable high performance but have long design cycle and scarce flexibility, while general-purpose processors present the opposite trade-off. Specialized programmable engines achieve some of the benefits of both approaches, but are still hard to program and limited either in terms of flexibility or performance.In this paper we investigate a different design point. Our solution, SWSL (SoftWare Synthesis for network Lookup) generates hardware logic directly from lookup applications written in C++. Therefore, it retains a simple programming model yet leads to significant performance and power gains. Moreover, compiled application can be deployed on either FPGA or ASIC, enabling a further trade-off between flexibility and performance. While most high-level synthesis compilers focus on loop acceleration, SWSL generates entire lookup chains performing aggressive pipelining to achieve high throughput.Initial results are promising: compared with a previously proposed solution, SWSL gives 2 − 4× lower latency and 3 − 4× reduced chip area with reasonable power consumption.

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“…When running today's memory intensive applications, modern computers spend most of their time and energy moving data rather than on computation, wasting energy. Further, today's systems are power limited [1], [18], [10], exacerbating the problem.…”

Section: Introductionmentioning

confidence: 99%

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

Zhu

Vaidyanathan

Shacham

et al. 2012

2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors

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This paper presents a design methodology for hardware synthesis of application-specific logic-in-memory (LiM) blocks. Logic-in-memory designs tightly integrate specialized computation logic with embedded memory, enabling more localized computation, thus save energy consumption. As a demonstration, we present an end-to-end design framework to automatically synthesize an interpolation based logic-inmemory block named interpolation memory, which combines a seed table with simple arithmetic logic to efficiently evaluate functions. In order to support multiple consecutive seed data access that is required in the interpolation operation, we synthesize the physical memory into the novel rectangularaccess smart memory blocks. We evaluated a large design space of interpolation memories in sub-20 nm commercial CMOS technology by using the proposed design framework. Furthermore, we implemented a logic-in-memory based computed tomography (CT) medical image reconstruction system and our experimental results show that the logic-in-memory computing method achieves orders of magnitude of energy saving compared with the traditional in-processor computing.

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Rethinking Digital Design: Why Design Must Change

Cited by 71 publications

References 16 publications

Design principles for packet parsers

Design principles for packet parsers

SWSL: SoftWare Synthesis for network Lookup

Design Automation Framework for Application-Specific Logic-in-Memory Blocks

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