Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

Navlakha, Nupur; Lin, Jyi-Tsong; Kranti, Abhinav

doi:10.1109/ted.2017.2662703

Cited by 34 publications

(18 citation statements)

References 27 publications

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“…Furthermore, we have included the non-local BTBT model to account for the tunnelling phenomenon observed in certain modes of operation [31]. We have calibrated the tunneling model by reproducing the results presented in [20] and also validated our simulation model using the results presented for a DRAM in [7]. For simplicity, we have not considered interface traps and tunneling through thin oxide in this work, similar to previous studies [6]- [9], [20]- [22].…”

Section: Device Structure and Simulation Modelsmentioning

confidence: 94%

“…The proposed DL-DRAM employs a misaligned doublegate architecture. In a typical misaligned-gate architecture, the backgate has a stronger control over storing charge carriers in the write operation and the frontgate has a stronger control over the current in the read operation [7]. Fabricating misaligned-gate structures is possible using electrical vernier shifting proposed in [27].…”

Section: Introductionmentioning

confidence: 99%

“…A vertical FinFET-like structure where the top gate has been removed using etching or chemical mechanical polishing can also be used [28]. After the top gate removal, the misalignment in the gates can be patterned using different gate masks [7]. In the proposed DL-DRAM, the device employs tunneling-based read mechanism for source workfunction φ s > 4.5 eV and driftdiffusion for source workfunction φ s < 4.5eV .…”

Section: Introductionmentioning

confidence: 99%

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Dopingless 1T DRAM: Proposal, Design, and Analysis

James

Saurabh

2019

IEEE Access

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In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by driftdiffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration. INDEX TERMS DRAM, dopingless, sense margin, retention time, charge plasma.

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Section: Device Structure and Simulation Modelsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dopingless 1T DRAM: Proposal, Design, and Analysis

James

Saurabh

2019

IEEE Access

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“…We have calibrated the simulation model using [48]. The same tunneling model has been used in [9], [10], [15], [17], [46], [49]. Further, it is important to mention that the purpose of this work is to demonstrate how DGTFETs can be modified and employed in logic function realizations, rather than examining the exact current and voltage values.…”

Section: B Simulation Modelmentioning

confidence: 99%

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Garg

Saurabh

2020

IEEE J. Electron Devices Soc.

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Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this paper, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET) is used. The structure is designed such that the band-to-band tunneling (BTBT) occurs at the boundary of these dual-material gates, rather than at the source-channel junction. Further, to realize the XNOR function, the gate-source and the gate-drain overlaps are used. The proposed DGTFET-based logic function implementations are able to modulate the current flow as per the required functionality, achieving an ON-state current by OFFstate current (ION /IOF F) ratio of order ∼ 10 9. Furthermore, it is demonstrated that a CMOS-type XNOR gate can be realized by combining the proposed XNOR and XOR functions in the pull-up and pull-down network, respectively.

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“…Enhanced gm value and high output resistance ensures high intrinsic gain of the device which is extremely important for any device to be deployed for analog applications like a common source amplifier circuit. Literature also suggests that TFET devices can be used in designing reliable and low power applications like SRAM, DRAM and inverter circuit [24][25][26]. Unlike MOSFETs, TFETs exhibit unidirectional conduction because of their asymmetric source and drain architecture [24,27].…”

Section: Rf and Analog Performance Analysismentioning

confidence: 99%

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

Dutta

Soni

Pattanaik

2018

IJET

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This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average subthreshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

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Retention and Scalability Perspective of Sub-100-nm Double Gate Tunnel FET DRAM

Cited by 34 publications

References 27 publications

Dopingless 1T DRAM: Proposal, Design, and Analysis

Dopingless 1T DRAM: Proposal, Design, and Analysis

Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

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