Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

Martina, Maurizio; Masera, Guido; Roch, Massimo Ruo; Piccinini, Gianluca

doi:10.1109/tcsi.2015.2437513

Cited by 19 publications

(8 citation statements)

References 25 publications

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“…It reduces 44.5% of the adders in a multistandard transform core design. A result-biased circuit for DA has been used in the filter architectures for computing the discrete wavelet transform; it leads to a 20% to 25% reduction in hardware [24].…”

Section: Review Of Fir Adaptive Filter Designsmentioning

confidence: 99%

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

Jiang

Liu

Jonker

et al. 2019

IEEE Trans. Circuits Syst. I

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In this paper, a fixed-point finite impulse response adaptive filter is proposed using approximate distributed arithmetic (DA) circuits. In this design, the radix-8 Booth algorithm is used to reduce the number of partial products in the DA architecture, although no multiplication is explicitly performed. In addition, the partial products are approximately generated by truncating the input data with an error compensation. To further reduce hardware costs, an approximate Wallace tree is considered for the accumulation of partial products. As a result, the delay, area, and power consumption of the proposed design are significantly reduced. The application of system identification using a 48-tap bandpass filter and a 103tap high-pass filter shows that the approximate design achieves a similar accuracy as its accurate counterpart. Compared with the state-of-the-art adaptive filter using bit-level pruning in the adder tree (referred to as the delayed least mean square (DLMS) design), it has a lower steady-state mean squared error and a smaller normalized misalignment. Synthesis results show that the proposed design attains on average a 55% reduction in energy per operation (EPO) and a 3.2× throughput per area compared with an accurate design. Moreover, the proposed design achieves 45%-61% lower EPO compared with the DLMS design. A saccadic system using the proposed approximate adaptive filterbased cerebellar model achieves a similar retinal slip as using an accurate filter. These results are promising for the large-scale integration of approximate circuits into high-performance and energy-efficient systems for error-resilient applications.

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Section: Review Of Fir Adaptive Filter Designsmentioning

confidence: 99%

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

Jiang

Liu

Jonker

et al. 2019

IEEE Trans. Circuits Syst. I

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show abstract

“…Among state-of-the-art circuit techniques, distributed arithmetic has been widely used in the area-efficient and low-cost signal processing applications for convolution [5,6], transforms [7,8] and filtering [9,10]. Besides, DA-based architecture is also exploited as an excellent technique for implementing approximate computing [11], which has recently emerged as a promising approach to the energy-efficient design of IoT-related systems [12].…”

Section: Introductionmentioning

confidence: 99%

A Variation-Aware Design Methodology for Distributed Arithmetic

Lu¹,

Duan²,

Halak³

et al. 2019

Electronics

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Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, new error resilient techniques for DA computation are urgently required to improve robustness against the process, voltage, and temperature (PVT) variations. This paper proposes a new in-situ timing error prevention technique to mitigate the impact of variations in DA circuits by providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the sign extension block and carefully gate-sizing. Therefore, least significant bit (LSB) computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Our approach is demonstrated on a 16-tap finite impulse respons (FIR) filter using the 65 nm CMOS process and the simulation results show that this design can still maintain high-accuracy performance without worst case timing margin, and achieve up to 32 % power savings by voltage scaling when the worst case margin is considered with only 9 % area overhead.

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“…In this way, to reestablish the first picture, the compacted picture is decoded, dequantized, and afterward a reverse DWT is performed. Since wavelet pressure intrinsically brings about a set of multi-goals pictures, it is appropriate to working with huge symbolism which should be specifically seen at various goals, as just the levels containing the required degree of detail should be decompressed [2,3]. The center of picture pressure unit is DWT.…”

Section: Introductionmentioning

confidence: 99%

Time and Area Efficient 2-D DWT using Multiplier-less Canonic Signed Digit Technique

Jain*,

Rushiya,

Singhai

2019

IJRTE

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A few models have been recommended for proficient VLSI usage of 2-D DWT for constant applications. It is disc overed that multipliers devour more chip zone and expands multifaceted nature of the DWT design. Multiplier-less equipment usage approach gives an answer for diminish chip region, lower equipment intricacy and higher throughput of calculation of the DWT design.The proposed design outline is (i) priority must be given for memory complexity optimization over the arithmetic complexity optimization or reduction of cycle period and (ii) memory utilization efficiency to be considered ahead of memory reduction due to design complexity of memory optimization method. Based on the proposed design outline four separate design approaches and concurrent architectures are presented in this thesis for area-delay and power efficient realization of multilevel 2-D DWT.In this theory a multiplier-less VLSI engineering is proposed utilizing new dispersed number juggling calculation named CSD. We show that CSD is an effective engineering with adders as the principle part and free of ROM, duplication, and subtraction. The proposed design utilizing CSD gives less postponement and least number of cut thought about the current engineering. The reenactment was performed utilizing XILINX 14.1i and ModelSim test system.

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Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT

Cited by 19 publications

References 25 publications

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

A Variation-Aware Design Methodology for Distributed Arithmetic

Time and Area Efficient 2-D DWT using Multiplier-less Canonic Signed Digit Technique

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