Resource Reservations in Shared-Memory Multiprocessor SoCs

Pérez, Clara Otero; Rutten, Martijn J.; Steffens, Liesbeth; Eijndhoven, J. van; Stravers, Paul

doi:10.1007/1-4020-3454-7_5

Cited by 8 publications

(2 citation statements)

References 17 publications

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“…For example, a typical modern DRAM module consists of 8 to 16 banks to achieve high throughput. To support such a DRAM module, the DRAM controllers in [3], [31] would need a transaction length of 1KB (or 512B, depending on configurations), which is too big for most general purpose CPU architectures. Therefore, these predictable DRAM controller designs are not available in most COTS DRAM controllers.…”

Section: Related Workmentioning

confidence: 99%

“…Some DRAM controllers, specially designed for predictable memory performance, solve this problem by forcing to access all DRAM banks-in a pipelined manner-at a time for each memory transaction, thereby eliminating the capacity variation [30], [3], [31]. Some of the DRAM controllers also provide native support for bandwidth regulation [3], [31], which allow them to analyze DRAM performance based on network calculus [12] as shown in [38]. While they may be acceptable for specialized hardware architectures such as the TM3270 media processor [40], however, they require a very large transaction length to accommodate many DRAM banks.…”

Section: Related Workmentioning

confidence: 99%

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Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms

Yun

Yao

Pellizzoni

et al. 2016

IEEE Trans. Comput.

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Memory bandwidth in modern multi-core platforms is highly variable for many reasons and it is a big challenge in designing realtime systems as applications are increasingly becoming more memory intensive. In this work, we proposed, designed, and implemented an efficient memory bandwidth reservation system, that we call MemGuard. MemGuard separates memory bandwidth in two parts: guaranteed and best effort. It provides bandwidth reservation for the guaranteed bandwidth for temporal isolation, with efficient reclaiming to maximally utilize the reserved bandwidth. It further improves performance by exploiting the best effort bandwidth after satisfying each core's reserved bandwidth. MemGuard is evaluated with SPEC2006 benchmarks on a real hardware platform, and the results demonstrate that it is able to provide memory performance isolation with minimal impact on overall throughput.

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Section: Related Workmentioning

confidence: 99%