Resource conscious prefetching for irregular applications in multicores

Khan, Muneeb; Hägersten, Erik

doi:10.1109/samos.2014.6893192

Cited by 7 publications

(4 citation statements)

References 13 publications

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“…VanderWiel and Lilja [27] propose moving the software prefetches to a dedicated programmable hardware prefetch controller, to reduce the associated overheads, but their analysis technique also only works for regular address patterns without loads. Khan et al [7,8] choose to instead insert software prefetches at runtime using a runtime framework for code modification. This allows prefetching to be done for applications where the source code is unavailable, and also gives access to runtime data, but limits access to static information such as types, and also adds overhead.…”

Section: Related Workmentioning

confidence: 99%

Software Prefetching for Indirect Memory Accesses

Ainsworth

Jones

2018

ACM Trans. Comput. Syst.

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Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads are used to bring data into the cache hierarchy just before being required. However, these are difficult to insert to effectively improve performance, and techniques for automatic insertion are currently limited. This paper develops a novel compiler pass to automatically generate software prefetches for indirect memory accesses, a special class of irregular memory accesses often seen in high-performance workloads. We evaluate this across a wide set of systems, all of which gain benefit from the technique. We then evaluate the extent to which good prefetch instructions are architecture dependent. Across a set of memory-bound benchmarks, our automated pass achieves average speedups of 1.3× and 1.1× for an Intel Haswell processor and an ARM Cortex-A57, both out-of-order cores, and performance improvements of 2.1× and 3.7× for the in-order ARM Cortex-A53 and Intel Xeon Phi.

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Section: Related Workmentioning

confidence: 99%

Software Prefetching for Indirect Memory Accesses

Ainsworth

Jones

2018

ACM Trans. Comput. Syst.

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“…This version shows the limits/potential of the compiler to make use of the available architectural registers. InO-SW-Prefetch is a software prefetch solution taken from the work of Khan et al [38,40] 1 . InO-SW-prefetch uses profiling to identify delinquent loads to prefetch and manually inserts prefetch instructions at the appropriate distance.…”

Section: Swoop Unrolling and Sw Prefetchingmentioning

confidence: 99%

“…Comparison of unrolling and software prefetching with SWOOP, with and without hardware prefetching enabled. We evaluate the benchmarks common in the work proposing a modern software prefetcher [38,40] and SWOOP.…”

Section: Related Workmentioning

confidence: 99%

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores

et al. 2018

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Increasing demands for energy efficiency constrain emerging hardware. These new hardware trends challenge the established assumptions in code generation and force us to rethink existing software optimization techniques. We propose a cross-layer redesign of the way compilers and the underlying microarchitecture are built and interact, to achieve both performance and high energy efficiency.In this paper, we address one of the main performance bottlenecks-last-level cache misses-through a softwarehardware co-design. Our approach is able to hide memory latency and attain increased memory and instruction level parallelism by orchestrating a non-speculative, execute-ahead paradigm in software (SWOOP). While out-of-order (OoO) architectures attempt to hide memory latency by dynamically reordering instructions, they do so through expensive, power-hungry, speculative mechanisms. We aim to shift this complexity into software, and we build upon compilation techniques inherited from VLIW, software pipelining, modulo scheduling, decoupled access-execution, and software prefetching. In contrast to previous approaches we do not rely on either software or hardware speculation that can be detrimental to efficiency. Our SWOOP compiler is enhanced with lightweight architectural support, thus being able to transform applications that include highly complex control-flow and indirect memory accesses.The effectiveness of our software-hardware co-design is proven on the most limited but energy-efficient microarchitectures, non-speculative, in-order execution (InO) cores, which rely entirely on compile-time instruction scheduling.

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“…This version shows the limits/potential of the compiler to make use of the available architectural registers. InO-SW-Prefetch is a software prefetch solution taken from the work of Khan et al [38,40] 1 . InO-SW-prefetch uses proiling to identify delinquent loads to prefetch and manually inserts prefetch instructions at the appropriate distance.…”

Section: Swoop Unrolling and Sw Prefetchingmentioning

confidence: 99%

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores

Tran

Jimborean

Carlson

et al. 2018

Proceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation

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Increasing demands for energy eiciency constrain emerging hardware. These new hardware trends challenge the established assumptions in code generation and force us to rethink existing software optimization techniques. We propose a cross-layer redesign of the way compilers and the underlying microarchitecture are built and interact, to achieve both performance and high energy eiciency. In this paper, we address one of the main performance bottlenecksÐlast-level cache missesÐthrough a softwarehardware co-design. Our approach is able to hide memory latency and attain increased memory and instruction level parallelism by orchestrating a non-speculative, execute-ahead paradigm in software (SWOOP). While out-of-order (OoO) architectures attempt to hide memory latency by dynamically reordering instructions, they do so through expensive, power-hungry, speculative mechanisms. We aim to shift this complexity into software, and we build upon compilation techniques inherited from VLIW, software pipelining, modulo scheduling, decoupled access-execution, and software prefetching. In contrast to previous approaches we do not rely on either software or hardware speculation that can be detrimental to eiciency. Our SWOOP compiler is enhanced with lightweight architectural support, thus being able to transform applications that include highly complex control-low and indirect memory accesses.

show abstract

Resource conscious prefetching for irregular applications in multicores

Cited by 7 publications

References 13 publications

Software Prefetching for Indirect Memory Accesses

Software Prefetching for Indirect Memory Accesses

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores

SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order cores

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