Resolving discrete emission events: A new perspective for detrapping investigation in NAND Flash memories

Fitting Cells Into a Narrow <inline-formula> <tex-math notation="LaTeX">$V_{T}$ </tex-math></inline-formula> Interval: Physical Constraints Along the Lifetime of an Extremely Scaled NAND Flash Memory Array

“…The phenomenon leads, first of all, to an average reduction of cell V T as time elapses during idle/bake periods [26]- [29], owing to a dominant neutralization of negative charge in the oxide. In addition to that, however, a nonnegligible statistical dispersion of the V T shift as a function of time has been clearly detected in decananometer Flash arrays [27], [30], [33], [34]. This dispersion, attributed mainly to variability in the amount, and even in the polarity, of the charge trapped in the tunnel oxide of the array cells, results in a broadening of the V T distribution, which is particularly relevant on cycled arrays, on account of charge trapping in the tunnel oxide arising from the electrical stress determined by P/E cycles.…”

“…Charge detrapping leads, in fact, to an average reduction of cell V T arising from the neutralization of negative charge in the oxide. However, owing mainly to variability in the number of trapped charges, a relevant statistical dispersion of the V T shift comes also into play, broadening the V T distribution [27], [30], [33], [34].…”

Investigation of the Program Operation of NAND Flash Cells With a Single-Electron Resolution

“…This allowed, first, to improve the understanding of the RTN and charge trapping/detrapping phenomenology [11], [12], [17], [18], [20], [21], with the consequent development of predictive models and optimization rules able to tackle the impact of these effects on the technology. More recently, the demonstrated possibility of detecting single-electron charging of cell FG in state-of-the-art technologies [22] opened the way for new experimental investigations of the physical processes affecting the FG charge, starting from the program operation.…”

Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories

“…Instabilities are mainly the result of charge detrapping from the tunnel oxide of the memory cells, giving rise to unwanted displacements of their V T during idle/bake periods [1][2][3][4][5][6][7][8]. Although the statistical nature of the detrapping process and, in turn, of the resulting V T shift (DV T ) has been clearly recognized [3,6,9,10], an average reduction of V T as time elapses is the typical feature of detrapping in Flash arrays, owing to a dominant neutralization of negative charge in the cell tunnel-oxide [3][4][5]7]. This negative DV T is particularly detrimental for multi-level devices where the increase of storage density is traded off with the reduction of noise margins [11].…”