ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing

Sarangi, Smruti R.; Liu, Wei; Torrellas, Josep; Zhou, Yuanyuan

doi:10.1109/micro.2005.28

Cited by 35 publications

(28 citation statements)

References 36 publications

(64 reference statements)

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“…ReSlice [45] reexecutes only the conflicting load and its dependent instructions, and RetCon [8] performs symbolic reexecution of simple, conflicting auxiliary updates (e.g., updates to shared counters that are not used elsewhere in the transaction). Unlike these schemes, COMMTM does not trigger conflicts to begin with, avoiding superfluous communication and serialization.…”

Section: Additional Related Workmentioning

confidence: 99%

Exploiting semantic commutativity in hardware speculation

Zhang¹,

Chiu²,

Sánchez³

2016

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Abstract-Hardware speculative execution schemes such as hardware transactional memory (HTM) enjoy low run-time overheads but suffer from limited concurrency because they rely on reads and writes to detect conflicts. By contrast, software speculation schemes can exploit semantic knowledge of concurrent operations to reduce conflicts. In particular, they often exploit that many operations on shared data, like insertions into sets, are semantically commutative: they produce semantically equivalent results when reordered. However, software techniques often incur unacceptable run-time overheads.To solve this dichotomy, we present COMMTM, an HTM that exploits semantic commutativity. COMMTM extends the coherence protocol and conflict detection scheme to support user-defined commutative operations. Multiple cores can perform commutative operations to the same data concurrently and without conflicts. COMMTM preserves transactional guarantees and can be applied to arbitrary HTMs.COMMTM scales on many operations that serialize in conventional HTMs, like set insertions, reference counting, and top-K insertions, and retains the low overhead of HTMs. As a result, at 128 cores, COMMTM outperforms a conventional eager-lazy HTM by up to 3.4× and reduces or eliminates aborts.

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Section: Additional Related Workmentioning

confidence: 99%

Exploiting semantic commutativity in hardware speculation

Zhang¹,

Chiu²,

Sánchez³

2016

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…A different mechanism for selective re-execution is to find the slice of instructions affected by a dependence violation [15]. The system proposed by Tuck and Tullsen [20] uses multiple contexts to recover from failed value prediction.…”

Section: Related Workmentioning

confidence: 99%

Increasing the energy efficiency of TLS systems using intermediate checkpointing

Khan¹,

Ioannou

Xekalakis

et al. 2011

2011 18th International Conference on High Performance Computing

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Abstract-With the advent of Chip Multiprocessors (CMPs), improving performance relies on the programmers/compilers to expose thread level parallelism to the underlying hardware. However, this is a difficult and error-prone process for the programmers, while state of the art compiler techniques are unable to provide significant benefits for many classes of applications. An alternative is offered by systems that support Thread Level Speculation (TLS), which relieve the programmer and compiler from checking for thread dependences and instead use the hardware to enforce them.Unfortunately, TLS suffers from power inefficency because data misspeculations cause threads to roll back to the beginning of the speculative task. For this reason intermediate checkpointing of TLS threads has been proposed. When a violation does occur, we now have to roll back to a checkpoint before the violating instruction and not to the start of the task. However, previous work omits study of the microarchitectural details and implementation issues that are essential for effective checkpointing.In this paper we study checkpointing on a state-of-the art TLS system. We systematically study the costs associated with checkpointing and analyze the tradeoffs. We also propose changes to the TLS mechanism to allow effective checkpointing. Further, we establish the need for accurately identifying points in execution that are appropriate for checkpointing and analyze various techniques for doing so in terms of both effectiveness and viability. We propose program counter based and hybrid predictors and show that they outperform previous proposals. Placing checkpoints based on dependence predictors results in power improvements while maintaining the performance advantage of TLS. The checkpointing system proposed achieves an energy saving of up to 14%, with an average of 7% over normal TLS execution.

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“…Although we do not rely on creating checkpoints in this work, we draw some inspiration from several recent proposals which use register file checkpointing and exploit load-independence to accelerate the execution of single-threaded applications [11,17,19]. There are some principal differences between our proposal and those prior works and it is important to highlight them.…”

Section: Register File Optimizationsmentioning

confidence: 99%

“…The key statistics that provided an inspiration for this work is that the majority of the instructions in the shadow of the long-latency loads are, in fact, load-independent [19]. These load-independent instructions release their issue queue entries fairly fast, but then pile up in the reorder buffer, waiting for the cache miss to be serviced.…”

Section: Introductionmentioning

confidence: 99%

An L2-miss-driven early register deallocation for SMT processors

Sharkey

Ponomarev

2007

Proceedings of the 21st Annual International Conference on Supercomputing

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The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow the use of smaller register files without degrading performance, techniques that maximize the efficiency of using registers through aggressive register allocation/deallocation can be considered. In this paper, we propose a novel technique to early deallocate physical registers allocated to threads that experience L2 cache misses. This is accomplished by speculatively committing the load-independent instructions and deallocating the registers corresponding to the previous mappings of their destinations, without waiting for the cache miss request to be serviced. The early deallocated registers are then made immediately available for allocation to instructions within the same thread as well as within other threads, thus improving the overall processor throughput. On the average across the simulated mixes of multiprogrammed SPEC 2000 workloads, our technique results in 33% improvement in throughput and 25% improvement in terms of harmonic mean of weighted IPCs over the baseline SMT with the state-of-the-art DCRA policy. This is achieved without creating checkpoints, maintaining per-register counters of pending consumers, performing tag re-broadcasts, register re-mappings and/or additional associative searches.

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ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing

Cited by 35 publications

References 36 publications

Exploiting semantic commutativity in hardware speculation

Exploiting semantic commutativity in hardware speculation

Increasing the energy efficiency of TLS systems using intermediate checkpointing

An L2-miss-driven early register deallocation for SMT processors

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