ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors

Qiu, Keni; Jao, Nicholas; Zhao, Mengying; Mishra, Cyan Subhra; Gudukbay, Gulsum; Jose, Sethu; Sampson, Jack; Kandemir, Mahmut; Narayanan, Vijaykrishnan

doi:10.1109/hpca47549.2020.00034

Cited by 27 publications

(7 citation statements)

References 37 publications

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“…ResiRCA [103] uses an adaptable RRAM crossbar accelerator for MAC (multiply+accumulate) operations for CNNs. The architecture is able to adapt to varying levels of input power to eiciently utilize the PIM components.…”

Section: Discussionmentioning

confidence: 99%

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Resch

Khatamifard

Chowdhury

et al. 2022

ACM Trans. Embed. Comput. Syst.

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Beyond edge devices can operate outside the reach of the power grid and without batteries. Such devices can be deployed in large numbers in regions which are difficult to access. Using machine learning, these devices can solve complex problems and relay valuable information back to a host. Many such devices deployed in low earth orbit can even be used as nano-satellites. Due to the harsh and unpredictable nature of the environment, these devices must be highly energy efficient, be capable of operating intermittently over a wide temperature range, and be tolerant of radiation. Here, we propose a non-volatile processing-in-memory (PIM) architecture which is extremely energy efficient, supports minimal overhead checkpointing for intermittent computing, can operate in a wide range of temperatures, and has a natural resilience to radiation.

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Section: Discussionmentioning

confidence: 99%

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Resch

Khatamifard

Chowdhury

et al. 2022

ACM Trans. Embed. Comput. Syst.

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“…Mapping homomorphic inference onto [77] would incur a large communication (read/write) overhead due to the required intra-array data movement. ResiRCA [72] uses in-memory computation to accelerate parts of ML inference and adapts the amount of parallelism to match the amount of harvested energy. However, they rely on a battery to maintain a controlling CPU.…”

Section: Power Limitationsmentioning

confidence: 99%

Towards Homomorphic Inference Beyond the Edge

Resch¹,

Chowdhury²,

Cılasun³

et al. 2021

Preprint

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Beyond edge devices can function off the power grid and without batteries, enabling them to operate in difficult to access regions. However, energy costly long-distance communication required for reporting results or offloading computation becomes a limitation. Here, we reduce this overhead by developing a beyond edge device which can effectively act as a nearby server to offload computation. For security reasons, this device must operate on encrypted data, which incurs a high overhead. We use energy-efficient and intermittent-safe in-memory computation to enable this encrypted computation, allowing it to provide a speedup for beyond edge applications within a power budget of a few milliWatts.

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“…While conventional ReRAM-based accelerators can significantly enhance the performance of NN accelerators, their power consumption is too much for energy harvesting nodes. Hence, ResiRCA [103] architecture is presented that combines an energy-efficient configurable ReRAM-based DNN inference engine with a battery-powered IoT node. It allows the accelerator to adapt to a given amount of harvested energy and operate accordingly.…”

Section: Nn Operations On Embedded Processorsmentioning

confidence: 99%

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

Nabavinejad

Baharloo

Chen

et al. 2020

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Deep Neural Networks (DNNs) have shown significant advantages in many domains, such as pattern recognition, prediction, and control optimization. The edge computing demand in the Internet-of-Things (IoTs) era has motivated many kinds of computing platforms to accelerate DNN operations. However, due to the massive parallel processing, the performance of the current large-scale artificial neural network is often limited by the huge communication overheads and storage requirements. As a result, efficient interconnection and data movement mechanisms for future on-chip artificial intelligence (AI) accelerators are worthy of study. Currently, a large body of research aims to find an efficient on-chip interconnection to achieve low-power and high-bandwidth DNN computing. This paper provides a comprehensive investigation of the recent advances in efficient on-chip interconnection and design methodology of the DNN accelerator design. First, we provide an overview of the different interconnection methods on the DNN accelerator. Then, the interconnection methods on the non-ASIC DNN accelerator will be discussed. On the other hand, with the flexible interconnection, the DNN accelerator can support different computing flow, which increases the computing flexibility. With this motivation, reconfigurable DNN computing with flexible on-chip interconnection will be investigated in this paper. Finally, we investigate the emerging interconnection technologies (e.g., in/near-memory processing) for the DNN accelerator design. This paper systematically investigates the interconnection networks in modern DNN accelerator designs. With this article, the readers are able to: 1) understand

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ResiRCA: A Resilient Energy Harvesting ReRAM Crossbar-Based Accelerator for Intelligent Embedded Processors

Cited by 27 publications

References 37 publications

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

Towards Homomorphic Inference Beyond the Edge

An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators

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