Resilient hardware Trojans detection based on path delay measurements

Abstract

International audienceA Hardware Trojan is a malicious hardware modification of an integrated circuit. It could be inserted at different design steps but also during the process fabrication of the target. Due to the damages that can be caused, detection of these alterations has become a major concern. In this paper, we propose a new resilient method to detect Hardware Trojan based on path delay measurements. First, an accurate path delay model is defined. Then, path delay measurements are compared in a way that theoretically eliminate process and experimental variations effects. Finally, this proposed detection method is experimentally validated using different FPGA boards with substantial process variations. Both small sized sequential and combinatorial Hardware Trojans are implemented and successfully detected

SoK

“…Clock glitches has been proposed in [56] to measure path delays for authenticating the FPGA IP block and detecting HT anomalies. Similarly, clock glitching method has been used in [28] to measure path delays, and various statistical techniques have been used to reduce the adverse effects of inter-die and intra-die process variations. In [24], Cui et al proposed a two-phase technique using the order of path delay in path pairs for HT detection.…”

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead

“…As a result, non-destructive methods are needed to provide post-fabrication tests on all the production before deployment in the field. Related approaches are classified into sidechannel analysis [14][15][16][17][18][19], logic testing [20][21][22][23][24][25][26][27] and visual inspection [28] (not present in Fig. 2).…”

“…Methods based on side channel analysis focus on monitoring physical characteristics such as power consumption [14], path delay [15][16][17] or electromagnetic energy [17]. The characteristics of the IC under evaluation are compared with the ones of "golden ICs" i.e.…”

Метод Исключения Переменной Из Кнф Цейтина

“…Разработка проверяющих и диагностирующих тестов занимает всѐ больше времени при проектировании цифровых устройств. Одной из актуальных проблем диагностики является получение тестовых наборов для обнаружения неисправностей задержек путей [1,2].…”