Research progress of radiation effects mechanisms and experimental techniques in nano-devices

Chen, Wei; Liu, Jie; Ma, Xiaojuan; Guo, Gang; Zhao, Yuanfu; Guo, Xiaoqiang; Luo, Y.; Yao, Zhibin; Ding, Lili; Wang, Chenhui; Chen, Rongmei; He, Bin; Zhao, Wei; Zhang, Fengqi; Ma, Wuying; Zhai, Pengfei; Wang, Zujun; Liu, Tianqi; Guo, Hongxia; Liu, Jiande; Yang, Hu; Hu, Peipei; Cong, Peitian; Li, Zongzhen

doi:10.1360/n972017-00771

Cited by 11 publications

(4 citation statements)

References 22 publications

(22 reference statements)

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“…For the advanced 65 nm CMOS-based EBRAM cells, SEU critical charge declined significantly when compared with sub-micron devices, making the unhardened unit more sensitive to heavy ion irradiation [9,10]. In addition, the carriers created by ionized ions could deposit enough energy in more than one drain regions of off-state MOSFETs in the vicinity, leading to a large MBU rate and high SEU cross section.…”

Section: Effectiveness Of Configuration Hardeningmentioning

confidence: 99%

“…Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) possesses plenty of flexible configuration switches and logics to implement million-gate circuits with a very short development time [1,2], which makes it a valuable Integrated Circuit (IC) for an electronic system. However, the Complementary Metal Oxide Semiconductor (CMOS) based architectures in SRAM-FPGA are very sensitive to radiation effects, which reduces the on-orbit safety and reliability [3][4][5][6][7][8][9]. Therefore, it is necessary to evaluate and mitigate the Single Event Effects (SEEs) of SRAM-based FPGAs for potential space applications.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, hardening technique selection is a tradeoff strategy among function, performance, area and radiation tolerance. For example, errors occurring in Configuration RAMs (CRAMs), which control the routing, the switches and the logic state of an FPGA, have the most critical impact on the FPGA function, and so that the radiation tolerance of CRAMs has to be high, although it costs non-negligible area and power [8][9][10][11]. Other resources, e.g.…”

Section: Introductionmentioning

confidence: 99%

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Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

et al. 2019

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The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 −13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 −15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.

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Section: Effectiveness Of Configuration Hardeningmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

et al. 2019

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“…Among them, single-event upset is the most common and typical, mainly occurring in components that store data or instructions. Component errors caused by single event upset belong to soft errors, which can be restored through system reset, reboot, or rewrite [4][5][6][7][8]. Single-event upset is relatively common in the aerospace field, due to long-term exposure of spacecraft to harsh space environments and susceptibility to high-energy particle interference [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

Single Event Effect Protection Design of Output Module of Relay Protection Device

Gao,

Ma,

Zhao

et al. 2024

J. Phys.: Conf. Ser.

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A design scheme for single event effect protection of output modules has been proposed, which combines software and hardware to solve the problem of output relay misoperation or refusal to operate caused by single event effect in the output module of relay protection devices. The core idea is to use dual path independent logic processing in software and dual circuit combination driving control in hardware to ensure that the output of the relay protection device will not misoperate when single event effects occur. The error detection and correction of instruction processing code is designed for MCU on-chip instruction storage areas that are easily affected by single event effects. It executes cyclically, allowing the output module to quickly return to normal after single-event effects occur, ensuring that the device output will not refuse to operate when it is expected to operate. When an irreparable error is detected, the output power supply is locked to ensure that the device output does not misoperate. Based on the experimental verification results, the reliability of the relay protection device is improved through the above methods.

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A simulation result of trapped charge in PPD CIS induced by total ionizing dose effect

Lai

Wang

Huang

et al. 2023

Nuclear Instruments and Methods in Physics Research Section A:

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Research progress of radiation effects mechanisms and experimental techniques in nano-devices

Cited by 11 publications

References 22 publications

Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

Single Event Effect Protection Design of Output Module of Relay Protection Device

A simulation result of trapped charge in PPD CIS induced by total ionizing dose effect

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