Research on Interface Properties of Thermally Grown SiO₂ and ALD SiO₂ Stacked Structures

Abstract

This study presents a stacked process of thermal and atomic layer deposition (ALD) SiO2 that reduces the interface trap density of 4H-SiC metal-oxide-semiconductor (MOS) capacitors. The channel mobility of metal-oxide-semiconductor field effect transistors are reduced due to the high interface trap density as well as coulomb scattering mechanism. Herein, we investigate SiO2/SiC interface properties of a stacked process, which is accomplished via reducing the thickness of thermal oxidation film. Notably, MOS capacitors fabricated with thermal and ALD SiO2 stacked structures can reduce the interface state density (Dit) by twofold at 0.2 eV below the conduction band energy compared with thermally grown SiO2. Furthermore, the interface state density decreases more steeply in the range of energy levels close to the conduction band. Additionally, the leakage current increases at a relatively slow rate in the electric field of 5 -10 MV/cm, whereas the leakage current increases sharply when the electric field is higher than 10 MV/cm. The resultant ALD SiO2 stacked structure provides a new approach to improving interface quality, which allows for a reduction in the thermal budget involved in the fabrication and preparation of devices.

The GaN trench MOSFET with adaptive voltage tolerance achieved through a dual-shielding structure

“…For SG, we considered parameters such as the distance to the bottom of the gate oxide layer (D ox ) and the distance to the sidewall of the gate oxide layer (L ox ). In this study, BV is defined as the drain voltage at which the impulse ionization integral equals 1 or the critical electric field (10 MV cm −1 ) for the ALD-deposited SiO 2 [18]. As D ps increases, the peak electric field in the gate oxide layer decreases, which indicates that the further P_shield is from P_base the more effective it is in suppressing the peak electric field (E oxide ) in the gate oxide layer and improving the reliability of the gate oxide layer.…”