Research on hot carrier reliability of n-MOSFET in deep submicron technology

Jia, Shen; Zhang, Ming; Tan, Can; Xue, Fei; Li, Wei

doi:10.1109/icct.2017.8359935

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…Furthermore, the high electric field in the channel near the drain region generates hot carriers in device layer. These hot carriers can inject into thin gate oxide through impactionization [26]. This causes the generation of charge traps and interface states and subsequently degrades the performance of the device in terms of GIDL and V th roll-off.…”

Section: Off State Behavior Analysismentioning

confidence: 99%

Reducing off-state leakage current in dopingless transistor employing dual metal drain

Zafar

Raushan

Ahmad

et al. 2019

Semicond. Sci. Technol.

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In this paper a new configuration for dopingless transistor is presented for preventing the off-state tunneling from channel to drain. In this work, workfunction engineering has been performed at drain electrode of the device. For this, drain electrode metal is divided into two sections. Workfunction of the drain section near the gate is kept at relatively higher value than the other section. This approach increases the tunnel barrier formed at the gate-drain interface which prevents the carries to tunnel from channel to drain in the off-state (V GS =0.0 V, V DS =1.0 V). Employing dual metal at drain electrode gives better control over channel which results in significant improvement in the electrical performance of the junctionless transistor. The I OFF for proposed dual metal drain (DMD) configuration is reduced by 5 orders which aids to improve I ON /I OFF ratio by 4 orders as compared to conventional for gate length 20 nm. The subthreshold slope and drain induced barrier lowering are also reduced by 4% and 35% respectively. The DMD device also exhibits reduced intrinsic capacitances (C gg and C gd ). To evaluate the performance, comparative analysis of the proposed device has been performed with dual metal gate and conventional transistors which have yielded considerable improvements. The gate length (L G ) scaling down to 5 nm has also been performed for the DMD configuration to demonstrate its advantages over conventional counterpart.

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Section: Off State Behavior Analysismentioning

confidence: 99%