Research on agile FPGA fault injection system

Zhang, Yaowei; Chen, Lei; Wang, Shuo; Zhou, Jing; Tian, Chunsheng; Feng, Hanxu

doi:10.1109/icm52667.2021.9664913

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…The works [33][34][35][36][37][38] present similar platforms for fault injection in CUT (or DUT) and can be used for the same purpose and also make use of the ICAP port for the injection of the faults. However, the works listed focus on evaluating the sensitivity to SEEs of SRAM-based FPGAs, not being focused on CUT.…”

Section: Related Workmentioning

confidence: 99%

“…Another limitation when comparing with these works is the FPGA used, since they all use different versions or families of FPGA, not allowing a fair evaluation to be made since issues such as area, primitives/resources, and structures of the CLBs are different. Despite this, the works by [36,37,39] explore the Triple Modular Redundancy (TMR) technique, as is explored in this work. It was also identified in work [36] about the exploitation of processors, but with RISC-V architecture.…”

Section: Related Workmentioning

confidence: 99%

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A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

et al. 2023

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Precise Fault Injection and Fault Location System for SRAM-based FPGAs

Feng

Liu

Chen

et al. 2022

2022 IEEE 10th Joint International Information Technology and Artificial Intelligence Conference (ITAIC)

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Stability Analysis of Surrounding Rock of an Underground Cavern Group and Excavation Scheme Optimization: Based on an Optimized DDARF Method

Daud

Yusoff

et al. 2023

Applied Sciences

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The surrounding rock stability of an underground cavern group is an important issue in the process of cavern excavation, which has the characteristics of large displacement, discontinuity and uneven deformation, so the calculation and analysis are very complicated. The optimized discontinuous deformation analysis for rock failure method was adopted to analyze the stability of the surrounding rock of a real underground engineering cavern group under different excavation schemes. The cracking process of surrounding rock under different excavation schemes, the depth of crack expansion and the vertical displacement of the arch and bottom floor were obtained, and the following conclusions are drawn: (a) After the completion of the excavation, the stability problems mainly appeared in the surrounding rocks of the arch, left wall, right wall and bottom floor of the main powerhouse, in the surrounding rocks of the arch, left wall and bottom floor of the main transformer chamber and in the surrounding rocks of the arch, right wall and bottom floor of the tailrace surge tank. (b) Fault f2 has an influence on the stability of the surrounding rock of the tailrace surge tank, while fault f1 has no influence on the stability of the cave group. (c) The scheme of simultaneous excavation of three caverns shows the advantages in the crack propagation depth of surrounding rock and vertical displacements of caverns.

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Research on agile FPGA fault injection system

Cited by 3 publications

References 10 publications

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

Precise Fault Injection and Fault Location System for SRAM-based FPGAs

Stability Analysis of Surrounding Rock of an Underground Cavern Group and Excavation Scheme Optimization: Based on an Optimized DDARF Method

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