Research of Synchronization Circuits for Digital Communication Systems

Abstract

In a digital communication system, the transmitter and receiver have several generators for modulation and demodulation; increasing and decreasing the sampling frequency; synchronization of symbols and bit streams. The causes of phase and carrier frequency errors are the instability of the frequency of the local generators of the transmitter and receiver; presence of Doppler frequency shift; signal propagation delay from the transmitter to the receiver. Synchronization circuits of modern digital communication systems are built on the basis of phase-locked loop (PLL). The purpose of the work is: research of various characteristics of the digital PLL (locking time; established error; transient behavior) for various types of input action; study of the bit error rate of a coherent digital communication system. The PLL consists of the following components: a phase detector that generates a signal that varies in proportion to the phase difference between the input signal and a locally generated sinusoid; controlled generator that generates an output signal whose phase and frequency depends on the input signal; loop filter, which removes unwanted high-frequency components in the output signal of the phase detector and forms a signal that controls the NCO. During adaptation, the PLL has some transient process that depends, in particular, on three factors: the presence of a zero-phase error is determined by the PLL contour filter; the determined bandwidth of the circuit and the initial deviation between the input and reference frequencies affect the PLL adaptation time; the attenuation coefficient of the PLL affects the adaptation behavior: the speed and magnitude of emissions. The study of the output signal of the linear PLL model for damping factor , and , and we will use an input signal of the step function type, linear voltage changes and hyperbola. type 1, type 2, and type 3 PLLs can adapt to a zero-error step input. If the input signal is a linearly varying voltage, PLL types 2 and 3 can adapt with zero phase error, while type 1 adapts with a residual phase error. For hyperbola input, only type 3 PLL can fully adapt: type 2 adapts with residual error, while type 1 cannot adapt. The damping factor should be in the range of . When changing the input signal frequency from 3.55 MHz to 3.72 MHz, the capture time of the type 2 PLL changes from about 150 μs to about 600 μs, that is, when the frequency increases by 170 kHz, the capture time increases almost four times. The error that has occurred is affected by the choice of the contour filter and the features of the synchronization.