Requirements of bipolar switching ReRAM for 1T1R type high density memory array

Yi, Jaeyun; Choi, Hyejung; Song, S.; Son, Donghee; Lee, Sangkeum; Park, Jin-Won; Kim, Wangee; Sung, Min-Gyu; Lee, Sung-Hoon; Moon, Jiwon; Kim, Choidong; Park, Jungwoo; Joo, Moon Sig; Roh, Jae–Sung; Park, Sung-Ki; Chung, Se-Kyo; Jeong, Jae-Goan; Hong, Seongin; Park, Sung Wook

doi:10.1109/vtsa.2011.5872232

Cited by 7 publications

(4 citation statements)

References 2 publications

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“…As expected, the 1T1R bitcell requires a huge gate overdrive to perform sub-100µsec reset time. As a reference, 1T1R bitcells demonstrated in the literature require more from 3 to 5V to enable sub-100ns reset operations [6] [7] [8]. Figure 15 presents the evolution of the programming time of the previously mentioned bitcells.…”

Section: Figure 14: Set Time Versus Bl-sl Voltage Difference For Minimentioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

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Section: Figure 14: Set Time Versus Bl-sl Voltage Difference For Minimentioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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“…Due to its relatively smaller write current compared to PCRAM, i.e. 100 μA for 54 nm 54 nm cell [22], an ReRAM based 1T-1R cell can be reduced to >20 in size. However, it has a low endurance 10 and >10 ns switching speed, limiting its applications [23].…”

Section: Emerging Memory Technologies With 1t-1r Cell Structurementioning

confidence: 99%

Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

Wang

Lee

Amiri

2015

IEEE Trans. Nanotechnology

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We introduce a magnetoelectric junction driven by voltage-controlled magnetic anisotropy (VCMA-MEJ) as a building block for a range of low-power memory application. We present and discuss specifically two applications, magnetoelectric random access memory (MeRAM) and ternary contentaddressable memory (TCAM). The MEJ differs from a magnetic tunnel junction (MTJ) in that electric field is used to induce switching in lieu of substantial current flow in MTJ. Electric-fieldcontrol of magnetism can dramatically enhance the performance of magnetic memory devices in terms of switching energy efficiency and switching speed. The development of such an energy-efficient and ultra-fast memory has a potential to change the paradigm of a hierarchical memory system in the conventional computer architecture. By combining speed, low power, and high density, electric-field-controlled magnetic memory combines features of multiple separate memory technologies used in today's memory hierarchy. The performance of a VCMA-MEJs based MeRAM, especially in the case of one access transistor associated with one MEJ (1T-1R) structure, is evaluated by comparing it with that of phase-change RAM (PCRAM), resistive RAM (ReRAM), and spin transfer torque RAM (STT-RAM). MeRAM can achieve ultra-fast switching (<1 ns), low switching energy (~1 fJ), and compact cell size of 4 with a diode access device, as well as nonvolatility. For another application, we propose the VCMA-MEJ based TCAM, which will be referred to as MeTCAM, consisting of 4T-2MEJs. Since MeTCAM fully exploits the low-power and highdensity features of the VCMA effect both in write and search operation modes, it obtains a fast searching speed (0.2 ns) with the smallest cell area ( ) compared to previous works.Keywords-non-volatile memory, voltage-controlled magnetic anisotropy (VCMA), magnetoelectric junction (MEJ), magnetic tunnel junction (MTJ), magnetoelectric random access memory (MeRAM), ternary content-addressable memory (TCAM)

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“…In the 1T1R topology [10], each ReRAM cell is in series with a selector transistor, which can optimally control the current flowing into the memory device. In a passive crossbar configuration [11], the top and bottom electrodes are directly connected to the bit and word line of the memory array.…”

Section: Introductionmentioning

confidence: 99%

“…5. The values used for the analysis were 10 for the LRS and 100 for the HRS, with a 10% additional resistance variability from those nominal values in order to compensate eventual resistance fluctuations. The read voltage used in the simulation is .…”

Section: ) Sneak-path Current Introductionmentioning

confidence: 99%

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

Sandrini

Barlas

Thammasack

et al. 2016

IEEE J. Emerg. Sel. Topics Circuits Syst.

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This work presents the co-integration of resistive random access memory crossbars within a 180 nm Read-Write CMOS chip.-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of-the-Line. Two different strategies, consisting in insertion of an tunnel barrier layer and the design of a dedicated CMOS read circuit, have been developed in order to increase the cell high-to-low resistance ratio of a factor of 1000 and to reduce the sneak-path current effects by one order of magnitude. The ReRAM cells have been integrated directly on a standard CMOS foundry chip, enabling low cost ReRAM-CMOS integration. The integrated memories show a set and reset voltages of and 1.3 V, respectively. The measured operating voltages are compatible for low-voltage applications.Index Terms-Heterogeneous integration, passive crossbar array, post-processing, read-write circuit, resistive ramdom access memories (ReRAMs).

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Requirements of bipolar switching ReRAM for 1T1R type high density memory array

Cited by 7 publications

References 2 publications

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Magnetoelectric Random Access Memory-Based Circuit Design by Using Voltage-Controlled Magnetic Anisotropy in Magnetic Tunnel Junctions

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology

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