Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

Vollenbruch, U.; Liu, Y.; Bauernfeind, Thomas; Pittorino, T.; Neubauer, V.; Mayer, Thomas; Maurer, Linus

doi:10.1109/mwsym.2006.249748

Cited by 11 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Literature provides several architectures and concepts for the feedback path [15]- [18]. These concepts can be separated by their complexity, required power consumption, required die area, and performance.…”

Section: Adpllmentioning

confidence: 99%

“…These concepts can be separated by their complexity, required power consumption, required die area, and performance. To demonstrate the potential of the ADPLL, Figure 18 shows the concept presented in [18], which can be obtained by a successive digitization of the fractional-N Figure 17. A comparison between the analog-intensive fractional-N PLL and the ADPLL shows that most of the analog blocks (colored green) can be replaced by digital implemented blocks (colored orange).…”

Section: Adpllmentioning

confidence: 99%

See 1 more Smart Citation

Be flexible

Maurer¹,

Stuhlberger²,

Wicpalek³

et al. 2008

IEEE Microwave

View full text Add to dashboard Cite

T raditionally, the cellular radio frequency (RF) transceiver market was dominated by bipolar complementary metal-oxide-semiconductor (BiC MOS)-based transceivers. While complementary metal-oxide-semiconductor (CMOS) was seen as a contending technology for some time, especially in the academic domain [1], the first products based on CMOS technology entered the cellular market only a few years ago [2]. Within a few years, the once-dominant position of SiGeBiCMOS technology was successfully tackled by CMOS, as depicted in Figure 1.This shift in technology favored a more "digital" centric transceiver partitioning, although the traditional analog architectures (e.g., direct-conversion receiver, direct modulation, or phase-locked loop (PLL)-based transmitters) remained. Sticking to the well-known analog architectures was possible, since 130 nm CMOS devices had enough headroom in terms of supply voltage and analog device performance. The ever-increasing requirements of multiband/multimode/multisystem cellular transceivers can be accommodated by utilizing the higher integration levels of digital blocks made possible with CMOS. Transceivers incorporating nine-band universal mobile telecommunications system (UMTS), including high speed downlink packet access (HSDPA) and high speed uplink packet access (HSUPA), quad-band global system for mobile communications (GSM)/general packet radio service (GPRS)/enhanced data rate for global evolution (EDGE) [4] are conceivable

show abstract

Section: Adpllmentioning

confidence: 99%

Section: Adpllmentioning

confidence: 99%

Be flexible

Maurer¹,

Stuhlberger²,

Wicpalek³

et al. 2008

IEEE Microwave

View full text Add to dashboard Cite

show abstract

“…A pure white quantization model for the TDC predicts only the phase-noise impact. In reality, the inclusion of a quantized phase detector in the loop brings in spurs when synthesizing close-to-integer frequencies [5]. In a conventional analog ΣΔ-PLL, the channel frequency dependent spurs are attributed to the insufficient scrambling of the ΣΔ output and a non-linear charge pump.…”

Section: Introductionmentioning

confidence: 99%

Analysis of fractional spur reduction using ΣΔ-noise cancellation in digital-PLL

Vengattaramane

Craninckx

Steyaert

2009

2009 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

In Digital Phase-Locked Loop based fractional-N RFfrequency synthesizers, the use of a Time-to-Digital Converter (TDC) as a quantized phase detector brings spurious emissions when synthesizing near-integer channel frequencies. The location of these fractional spurs is dependant on the resolution of the phase detector and the channel frequency being synthesized. In addition, spurs are also generated due to the non-uniform TDC quantization steps. This paper discusses a fast PLL simulation platform and a simulative analysis of the impact of ΣΔ-noise cancellation on the fractional spurs. I.978-1-4244-3828-0/09/$25.00 ©2009 IEEE

show abstract

“…The LPI-TDC resolution translates to quantization noise which limits the ADPLL performance [20]. The single-side band phase noise spectrum is defined by (4.25)…”

Section: Figure Of Meritmentioning

confidence: 99%

A 5GHz Passively Interpolated 5-Bit Time-to-Digital Converter with 8ps Resolution in IBM 130nm CMOS

Kidisyuk¹

View full text Add to dashboard Cite

This work demonstrates the development of a 5-bit time to digital converter (TDC) using the local passive interpolation (LPI) technique. The TDC architecture achieves a high resolution, while maintaining a low conversion latency, and a good linearity over process variation at multi-GHz rate of operation, which simplifies the calibration process. The time-to-digital converter was fabricated in a 0.13 µm IBM CMOS process (CMRF8SF). At a sampling rate of 100 MHz the maximum frequency of operation was measured to be 1.6 GHz. The uncalibrated resolution of 8.1 psec and a dynamic range of 260 psec were measured. The TDC is compatible with loop counter architectures that can further extend its dynamic range. The raw integral (INL) and differential (DNL) non-linearity of 1.02LSB and 0.52LSB respectively were observed. A correlation with the simulated results confirmed that the proposed LPI-TDC can operate at 5 GHz with some adjustments to measurement setup, input matching, and the on-chip supply integrity. I am deeply grateful to all the people who in one way or another have supported me during my Masters of Applied Science thesis. This academic research has been an invaluable experience, which has embarked me on a path to continue exploring integrated ciruits in the future. In particular, I would like to acknowledge Professor John W.M. Rogers and Professor Calvin Plett at Carleton University for their technical assistance in the research and writing of this thesis. Their oversight and feedback has allowed me to grow immensly, both professionally and as a researcher. The valuable guidance has created a firm foundation for all my future endeavours. I would also like to extend a special thank you to Nagui Mikhail for ensuring the testing phase of my research went smoothly and that I had all the components and equipment required. To my family and friends, thank you for your encouragement and support during this process, without which, this undertaking would not have been possible.

show abstract

Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

Cited by 11 publications

References 5 publications

Be flexible

Be flexible

Analysis of fractional spur reduction using ΣΔ-noise cancellation in digital-PLL

A 5GHz Passively Interpolated 5-Bit Time-to-Digital Converter with 8ps Resolution in IBM 130nm CMOS

Contact Info

Product

Resources

About

Requirements for Time-to-Digital Converters in the context of digital-PLL based Frequency Synthesis and GSM Modulation

Cited by 11 publications

References 5 publications

Be flexible

Be flexible

Analysis of fractional spur reduction using &#x03A3;&#x0394;-noise cancellation in digital-PLL

A 5GHz Passively Interpolated 5-Bit Time-to-Digital Converter with 8ps Resolution in IBM 130nm CMOS

Contact Info

Product

Resources

About

Analysis of fractional spur reduction using ΣΔ-noise cancellation in digital-PLL