Replacement Policies for a Function-Based Instruction Memory: A Quantification of the Impact on Hardware Complexity and WCET Estimates

Abstract

Instruction memories have a large influence on the timing behavior of hard real-time systems. Thus, to obtain safe and tight WCET estimates the instruction memory has to be predictable. Instruction memories in embedded real-time systems range from scratchpads with fixed content to dynamically managed fine-grained caches. In this paper we focus on a function-based dynamic instruction memory (D-ISP) and examine different replacement policies. We show their influence on the timing behavior of a hard real-time system and the complexity of a hardware implementation. A timing analysis unveils that a stack-based replacement policy reaches similar WCET estimates as LRU, especially for small scratchpad sizes. But in contrast to the stack-based replacement policy, LRU cannot be implemented with a reasonable amount of resources. Whereas, an experimental implementation of the proposed stack-based replacement policy needs only up to 23% more resources than a FIFO implementation.

A Method Cache for Patmos

“…Metzlaff and Ungerer present a comparison between different replacement strategies for the D-ISP with regard to the WCET [10]. FIFO-replacement, LRU-replacement, and stack replacement policies are compared.…”

Patmos: a time-predictable microprocessor

“…CarCore supports a single hard real-time thread to be executed with several non-real-time threads running concurrently in the background. The real-time thread uses a dynamic instruction scratchpad [41] that caches full functions. This approach is like the method cache [51] used in JOP [52] and in Patmos.…”