Removing user specified false paths from timing graphs

Abstract

We present a new method for removing user-specified

On timing-independent false path identification

“…Column 2 is the number of prime false path segments acquired with the proposed method. We then feed these segments into an ATPG engine built on top of an academic tool Atalanta [7] to check whether we can find a 1 PrimeTime can report true critical path delay with its own FPI feature.…”

“…As shown in Fig. 4, let us consider the propagation of S-Frontier from node F(1) to node G (1). Since the oninput of node G is non-controlling value, we also need to assign B with logic '1' and add the implication {B(1) → FF0(1)} into the implied cube.…”

“…For example, static timing analysis (STA) is an integral part in the physical design optimization process (e.g., timing-driven placement) for today's IC designs, used extensively to achieve circuit timing closure. Optimizing false paths, however, does not help to improve the performance of the circuit and the associated cost of optimization and iteration is expensive [1]. Similarly, targeting false paths during manufacturing test is unnecessary and may lead to over-testing of the circuit [9].…”

RTL analysis and modifications for improving at-speed test

“…False paths are untestable and excluding them improves the accuracy of analysis [2]. At the RTL our goal is to remove paths from fan-in registers of a capture register that are not in its functional support.…”

False timing path identification using ATPG techniques and delay-based information

“…Chang and Abraham proposed a path sensitization method [4]. Once false path sections have been identified, there are algorithms identifying them from the timing graph [2] [3]. Binary Decision Diagram(BDD)-based model checking and bounded SAT techniques were used at resolving false paths in synthesized logic blocks in [7].…”