Removing the overhead from software-based shared memory

Abstract. The gap between CPU peak performance and achieved application performance widens as CPU complexity, as well as the gap between CPU cycle time and DRAM access time, increases. While advanced compilers can perform many optimizations to better utilize the cache system, the application programmer is still required to do some of the optimizations needed for efficient execution. Therefore, profiling should be performed on optimized binary code and performance problems reported to the programmer in an intuitive way. Existing performance tools do not have adequate functionality to address these needs. Here we introduce source interdependence profiling, SIP, as a paradigm to collect and present performance data to the programmer. SIP identifies the performance problems that remain after the compiler optimization and gives intuitive hints at the source-code level as to how they can be avoided. Instead of just collecting information about the events directly caused by each source-code statement, SIP also presents data about events from some interdependent statements of source code. A first SIP prototype tool has been implemented. It supports both C and Fortran programs. We describe how the tool was used to improve the performance of the SPEC CPU2000 183.equake application by 59 percent.

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“…We also plan to incorporate this tool into DSZOOM [13], a software distributed shared memory system.…”

Section: Discussionmentioning

confidence: 99%

SIP: Performance Tuning through Source Code Interdependence

Berg

Hägersten

2002

Euro-Par 2002 Parallel Processing

Self Cite

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“…There has been substantial work on providing caching in software, including [14,22,24,18,25]. Most of the previous work focuses on caching data and providing coherence for a software implementation of distributed shared memory in a network of processors.…”

Section: Related Workmentioning

confidence: 99%

Orchestrating data transfer for the cell/B.E. processor

Chen

Lin

Zhang

2008

Proceedings of the 22nd Annual International Conference on Supercomputing

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“…There has been substantial work on providing caching in software, including [33,34,35,36]. Most of the previous work focuses on caching data and providing coherence for a software implementation of distributed shared memory in a network of processors.…”

Section: Related Workmentioning

confidence: 99%

Optimizing Compiler for the CELL Processor

Eichenberger¹,

O’Brien²,

Wu³

et al. 2005

14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05)

122

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Developed for multimedia and game applications, as well as other numerically intensive workloads, the CELL processor provides support both for highly parallel codes, which have high computation and memory requirements, and for scalar codes, which require fast response time and a full-featured programming environment. This first generation CELL processor implements on a single chip a Power Architecture processor with two levels of cache, and eight attached streaming processors with their own local memories and globally coherent DMA engines. In addition to processor-level parallelism, each processing element has a Single Instruction Multiple Data (SIMD) unit that can process from 2 double precision floating points up to 16 bytes per instruction. This paper describes, in the context of a research prototype, several compiler techniques that aim at automatically generating high quality codes over a wide range of heterogeneous parallelism available on the CELL processor. Techniques include compiler-supported branch prediction, compiler-assisted instruction fetch, generation of scalar codes on SIMD units, automatic generation of SIMD codes, and data and code partitioning across the multiple processor elements in the system. Results indicate that significant speedup can be achieved with a high level of support from the compiler.

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Removing the overhead from software-based shared memory

Abstract: The implementation presented in this paper-DSZOOM-WF

Cited by 14 publications

References 47 publications

SIP: Performance Tuning through Source Code Interdependence

SIP: Performance Tuning through Source Code Interdependence

Orchestrating data transfer for the cell/B.E. processor

Optimizing Compiler for the CELL Processor

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