Removable tape using thermoplastic adhesive for QFN assembly process

Kawai, Toshio; Nagoya, Toshio; Matsuura, Hidefumi

doi:10.1109/iemt.2002.1032750

Cited by 7 publications

(3 citation statements)

References 2 publications

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“…The package has EMC surface facing up with exposed lead/die pad at the bottom (Yan and Ramalingam, 2016). QFN is inexpensive and is being widely used in the semiconductor industry (Kawai et al, 2002;Lu et al, 2000) . A QFN package is small, thin and lightweight with low lead inductance.…”

Section: Introductionmentioning

confidence: 99%

In depth study of lead frame tape residuein quad flat non-leaded package

Nadaraja

Yap²

2019

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Purpose Lead frame tape is a crucial support for lead frames in the IC assembly process. The tape residue on the quad flat non-leaded (QFN) could result in low reliability and failure in electrical conductivity tests. The tape residue would affect overall performance of the chips and contribute to low pass yield. The purpose of this paper is to present an in-depth study of tape residue and factors that may affect it. Design/methodology/approach An experiment using lead frame and tapes from three manufacturers with two types of die bond adhesives, namely, die attach film (DAF) and wafer back coating (WBC), was conducted. Copper (Cu) wire bonding and die bonding performances were measured in terms of process capability, stitch bond strength and die attach strength. Findings Results showed that no tape residue was observed on the thermoplastic adhesive-based lead frames manufactured by Hitachi after the de-taping process because of the tape’s thermoplastic adhesive properties. Originality/value This paper studies the occurrence of tape residue and a viable solution for it through the correct process optimization and combination of semiconductor manufacturing materials. Factors that may affect tape residue have also been studied and further research can be done to explore other options in the future as an alternate solution.

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Section: Introductionmentioning

confidence: 99%

In depth study of lead frame tape residuein quad flat non-leaded package

Nadaraja

Yap²

2019

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“…Interconnections through component leads arranged at the periphery of the component have reached the limit of increasing demands in miniaturization and functional density. The QFN package provides solutions for this, and its use has increased significantly, driven by market demand (Kawai et al , 2002; Tee and Pascual, 2007; Huang and Lin, 2013). It is a plastic encapsulated lead-frame-based chip scale package with the lead pad on the bottom of the package to provide electrical interconnectivity with the PCB.…”

Section: Introductionmentioning

confidence: 99%

A grey-ANN approach for optimizing the QFN component assembly process for smart phone application

Huang

Chen

Lin

2016

SSMT

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Purpose This paper aims to propose an innovative parametric design for artificial neural network (ANN) modeling for the multi-quality function problem to determine the optimal process scenarios. Design/methodology/approach The innovative hybrid algorithm gray relational analysis (GRA)-ANN and the GRA-Entropy are proposed to effectively solve the multi-response optimization problem. Findings Both the GRA-ANN and the GRA-Entropy analytical approaches find that the optimal process scenario is a stencil aperture of 57 per cent and immediate processing of the printed circuit board after exposure to a room environment. Originality/value A six-week confirmation test indicates that the optimal process has improved quad flat non-lead assembly yield from 99.12 to 99.78 per cent.

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“…This trend has accelerated the need for continuous miniaturization within the integrated circuit (IC) packaging industry. The packaging technology of quad flat non‐lead (QFN), also known as MicroLeadFrame (MLF), provides solutions with regard to this and has increased significantly in terms of market demand (Kawai et al , 2002). The QFN package is a plastic encapsulated lead‐frame based chip scale package (CSP) with the lead pad on the bottom of the package to provide electrical interconnectivity with the printed circuit board (PCB).…”

Section: Introductionmentioning

confidence: 99%

Applying CHAID algorithm to investigate critical attributes of void formation in QFN assembly

Huang

Lin²

2013

Soldering & Surface Mount Tech

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PurposeThe purpose of this paper is to employ data mining as a new diagnosing scheme for investigating void formation to the thermal pad in quad flat non‐lead (QFN) assembly. Occurrences of voiding in various scenarios of component design, materials selection and manufacturing process are analyzed.Design/methodology/approachThis research investigates the process yield of a PCB assembly for a handheld device in the electronics manufacturing industry using the chi‐square automatic interaction detection (CHAID) algorithm and chi‐square test. Practical data generated by an X‐ray apparatus from the shop floor are collected. The critical attributes to the void formation (in the solder joint) of the QFN component are identified.FindingsStocking the PCB material beyond ten days may increase the level of voiding by 1%. Using PCB provided by vendor U helps decrease the level of voiding by 1.6%. Stocking the component material above 43 days may increase the level of voiding by 1.9%. In addition, reflow soldering profile with time above liquid (TAL) less than or equal to 62 sec and with peak temperature higher than or equal to 241°C generate less voids. Finally, the via‐in‐pad design causes a concave geometry on the surface of thermal pad which contributes to the voiding formation. The amount of voiding can be further diminished by plugging the via with plated copper.Originality/valueThis research implements CHAID that extracts useful knowledge from a huge amount of manufacturing data in order to realize the complex interaction effects through automated analysis. The extent of voiding in the samples using the optimal process suggested through CHAID algorithm can be reduced from 16% to 10.2%.

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Removable tape using thermoplastic adhesive for QFN assembly process

Cited by 7 publications

References 2 publications

In depth study of lead frame tape residuein quad flat non-leaded package

In depth study of lead frame tape residuein quad flat non-leaded package

A grey-ANN approach for optimizing the QFN component assembly process for smart phone application

Applying CHAID algorithm to investigate critical attributes of void formation in QFN assembly

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