Reliability Investigation of 1 Micron Depletion Mode IC MESFETs

Abstract

A BSTRACT A 1.6 eV activation energy has been observed for gate degradation of GaAs MESFETs fabricated with a commercially available 1 micron depletion mode IC process. Data from deep level transient spectroscopy (DLTS) and capacitance-voltage (C-V) measurements are consistent with a failure mechanism of gate metal interdiffusion into GaAs resulting in a decrease of channel thickness. The median life at 290°C channel temperature (TCH) was 80 hours, with a lognormal sigma of 0.7. Using these values, the projected FET failure rate is less than 0.01%/l000 hours (100 FIT) during the first million hours of life at T0 =150°C. SUMNIA RY1985 m3arked the first year that GaAs integrated circuits were available from several commercial sources in substantial volume [l]. With GaAs ICs now available from more than 10 companies world wide, it becomes increasingly important to understand the failure mechanisms and to demonstrate that GaAs IC technology can produce reliable products. Preliminary reliability study results of individual elements of a GaAs IC process have been previously reported [2]. Additional reliability tests on the key element, MESFETs, have been completed, and are reported in this paper, specif ically:As part of the failure analysis, deep level transient spectroscopy (DLTS) and capacitance-voltage (C-V) measurements were performed on long gate (1O0um x lO0um) FETs, baked at 285 0C for 370 hours, unbaised. The C-V data indicated that the carrier concentration was reduced by 28%, which is consistent with the observed electrical parameter changes. The DLTS data indicated that minimal changes were occuring in the trap concentration and no change in the trap energy level during the high temperature bake. The observed DC parameter changes, and the C-V and DLTS results are consistent with a failure mechanism of gate metal interdiffusion into the GaAs, resulting in the effective channel thickness being reduced. 2.FETs, lifetested for 1000 hours at T 175°C, exhibited little DC parameter drift.The maximum changes (3 standard deviations) observed for IDSS' VP and gm were 4%, 6%, and 5% respectively. EXPERIMENTAL PROCEDURE Test DevicesThe devices lifetested are FETs with 300um gate widths, physically laid out as 5 interdigitated 60-um fingers, (see Fig. 1). These devices were fabricated with a 1-um, depletion mode IC process [3]. A summary of this process is:1. Lifetests on 116 FETs at channel temperatures TCH=245, 260, 275, 290, and 310°C fabricated with a 1-um depletion mode IC process [3]. The objective of these lifetests was to find the median life values, the activation energy, and the failure mechanism(s).2. 1000 hour lifetest on FETs at TCH-175°C , fabricated with the same process. The objective of this lifetest was to evaluate FET parameter drift.All of the lifetests were conducted using the same hybrid lifetest fixture, designed to achieve TCH up to 310°C, yet suppress spurious oscillations which often occur with GaAs FETs. DC parameters were measured during the lifetest on a 1--3--10 hour sequence.The lifetest ...

Failure Mechanisms in GaAs ICs: The Effects of Deep Traps

“…Nevertheless, it is clear from this technique that the initial mobility near the surface of the devices without p layers reflects some initial compensation. We estimate that the compensation ratio (ND1 -NAi)/n (total ionized donors and acceptors divided Neglect of this effect results in conclusions about trap concentrations which cannot be trusted[26]. Following the analysis of Steivenard and Vuillaume [271, we use the measured carrier concentration to calculate numerically the conduction band profile at bias points used for the profiling measurement, accounting for edge effects in the presence of nonuniform background dopant concentrations.…”