Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults

Li, Jin-Fu; Tseng, Tsu-Wei; Hou, Chih-Sheng

doi:10.1109/tvlsi.2009.2022363

Cited by 11 publications

(3 citation statements)

References 22 publications

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“…A small difference in the ground voltages has applied for the write operation to detect the defects in memory [10]. Ensuing operations on the same cells giving higher aging effect and reducing reliability should be condensed [11]. Precharge voltage minimized to reduce the power in normal operations of the memory [12].…”

Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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The efforts in the semiconductor industry lead to the up-gradation of device size and performance of the devices. Extensive use of cache memory with significant size has become the requirement of most devices, applications, and gadgets. Advanced nanotechnology has resulted in scaled devices and more components with complex circuitry on system-on-chip. The memories are placed incredibly more profound in the die, and memory pins are not accessible readily, leading to more complications in testing the memories. The manufacturing of scaled devices is also a challenging task. A slight variation in doping concentration or process, supply voltage, temperature variations leads to faults in the memory. Advanced technology has increased the possibilities of occurrences of resistive defects in memories. For the smooth operation of systems with high reliability, it is essential to detect all the defects in the memory. In this paper, the detection of resistive defects is proposed at an early stage to increase the life span of the memory cells. Feeble cell detected at an early stage inhibits the more mutilation of the cells and improves memory reliability. An extensive range of defective values is used to analyze the proposed method to cover all positions of the defects in the cell. The proposed method detects the resistive defects with a minimum test time of 81.95μs for 4KB of the memory and contributes a negligible area overhead of 0.77%.

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Section: Introductionmentioning

confidence: 99%

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Mali¹,

Tak-Barekar²

2021

JUSST

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“…In [67], the authors propose a simple method to improve the reliability of a SRAM. The method proposed prevents a SRAM from executing successive multiple read operations on the same position.…”

Section: Self-healing Memory Systems Through Error Detection and Corr...mentioning

confidence: 99%

“…Then the defective element is replaced by the corresponding reconfiguration spare element. In [67], a new BISR scheme is proposed, which includes, besides BIST and the reconfiguration mechanism, the reliability-enhancement circuit and a test collar. The test collar is used to switch the RAM between BISR mode and normal mode (done by multiplexers).…”

Section: Self-healing Memory Systems Through Error Detection and Corr...mentioning

confidence: 99%

Self-healing and secure low-power memory systems

Neagu

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The main objective of this thesis is to bring new contributions to the self-healing and secure systems domain. In particular, to develop a self-healing technique for memory systems and to increase security of memory systems, techniques which favor low-power consumption. In order to achieve the main objective, three major research objectives were proposed: design of an error detection and correction scheme for errors that occur in memory systems and integrate them in a memory system, design techniques to increase the security and data privacy of memory systems against different types of attacks and to combine the previous two into a single solution, in order to achieve a self-healing and secure low-power memory system. The low-power aspect of the proposed solutions and techniques is evaluated during design stage and afterwards through simulation. Also, the architectures are evaluated from several other points of view, such as error detecting and correcting performance, area and delay overhead, and security efficiency. The first chapter contains a short introduction of the domain and subject of the thesis, current state of the art in this domain, proposed objectives and thesis organization. The second chapter contains a unidirectional error detecting, correcting and localization scheme, which is used for the self-healing technique. The chapter begins with an introduction and motivation about error detecting and correcting codes and their usage in memory systems and continues with a theoretical background. The chapter continues with the design of the proposed codes, which are explained in detail and illustrated through several figures. Then, they are analyzed from the following points of view: coding scheme, error localization, error correction and error escapes. For the latter three, metrics are defined, in order to evaluate the codes. Afterwards, the implementation of the proposed codes is exposed in several figures. Also, the usage of the codes is explained, as well as DRAM repair strategies. In the end of this chapter, the efficiency of the proposed codes is evaluated and exemplified. The evaluation process contains other metrics: speed and delay, area overhead, power consumption and code redundancy. Chapter 3 contains a proposed scheme to increase security in memory systems against cold-boot attacks. The technique uses data scrambling, hence the chapter begins with a short theoretical background and a review of data scrambling methods. It continues with the proposed solution, which is based on using unique scrambling vectors in an interleaved way, and theoretical performance and efficiency. The chapter ends with evaluation and experimental results for the proposed methodology. Evaluations of area overhead, power consumption and access time are performed in the CACTI simulation tool and on a FPGA development board. Chapter 4 approaches specific types of threats that can prevail in memory systems: simple and differential power or electromagnetic analysis attacks (SPEMA and DPEMA). The chapter begins with short introduction and motivation sections, and continues with a theoretical background about possible threats. In the following section, SPEMA and DPEMA are explained and discussed in detail. Afterwards, the proposed solutions for mitigating SPEMA and DPEMA are exhibited, and ends with evaluation and experimental results. An information leakage function is defined and used in evaluating the security efficiency of the solutions. The implementation costs are assessed with the use of the CACTI simulation tool, with respect to area and delay overhead, and power consumption. The final chapter, 5, contains the conclusions of the work, scientific contributions and future research directions.

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Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

Tak

Mali

2021

Lecture Notes in Electrical Engineering

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Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults

Cited by 11 publications

References 22 publications

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Non-Destructive Vector Fault Locator to Detect Resistive Open Defects in Static Random Access Memory with Improved Performance

Self-healing and secure low-power memory systems

Efficient Resistive Defect Detection Technique for Performance Enhancement of Static Random Access Memory

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