Reliability enhanced SiC MOSFET with partially widened retrograde P‐well structure

Abstract

In this Letter, a 1.2 kV SiC power MOSFET with a partially widened retrograde P-well (RP) structure and N-implanting region is proposed to enhance the device's reliability. Compared with the conventional SiC power MOSFET, the short circuit (SC) ability of the proposed structure can be improved effectively without sacrificing other performance. Simulation results reveal that a 40% reduction of the SC saturation current can be achieved, resulting in the SC withstand time increase from 7 to 10 μs at the DC-link voltage 800 V. Moreover, a better gate oxide reliability at 1.2 kV blocking condition also can be achieved. The peak electric field at the gate oxide interface is decreased by ∼48% owing to the shielding effect of the RP structure. In addition, the fabrication technology of the proposed structure is compatible with the standard planar SiC MOSFET manufacture process only with a few additional implanting steps. Therefore, this new MOSFET structure provides a simple and effective way to optimise the reliability of the planar SiC power MOSFET.

Characteristics prediction on SiC MOSFET implemented with BP neural network

“…Maximum working temperature of the SiC integrated circuits can reach 500°C [2] . More important, the SiC metal-oxidesemiconductor field-effect transistors (MOSFETs) and Schottky diodes are widely used in automobile industry [3] . In recent years, digital twin technology and artificial intelligence (AI) technique has been developed rapidly and are used more widely [4] .…”