Reliability-aware design for nanometer-scale devices

Abstract

Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges to maintain manufacturing yield rates and reliable devices in their expected lifetimes for latest nanometer-scale dimensions. In fact, new system and processor microarchitectures require new reliability-aware design methods and exploration tools that can face these challenges without significantly increasing manufacturing cost, reducing system performance or imposing large area overheads due to redundancy. In this paper we overview the latest approaches in reliability modeling and variability-tolerant design for latest technology nodes, and advocate the need of reliabilityaware design for forthcoming consumer electronics. Moreover, we illustrate with a case study of an embedded processor that effective reliability-aware design can be achieved in nanometer-scale devices through integral design approaches that covers modeling and exploration of reliability effects, and hardware-software architectural techniques to provide reliability-enhanced solutions at both microarchitectural-and system-level.

Proactive temperature balancing for low cost thermal management in MPSoCs

“…In [20], it is shown that aggressive power management can adversely affect reliability due to fast thermal cycles, and the authors propose an optimization method for MPSoCs that saves power while meeting reliability constraints. A HW-SW emulation framework for reliability analysis is proposed in [2], a reliability-aware register assignment policy is introduced as a case study.…”

Thermal-Aware Compilation for Register Window-Based Embedded Processors

“…The experimental work conducted has been performed using the hardware-software (HW-SW) emulation platform presented in [20]. This platform is required to extract the power traces corresponding to the execution of the application.…”

“…Based on the thermal traces collected for different benchmarks, it is observed that the thermal profile of the device is improved when the registers are assigned from spread spots of the RF, reducing in this way the mutual diffusion effect [20]. Based on this observation, register reallocation policies should be designed in order to allocate physically non-adjacent registers.…”

Temperature-Aware Design and Management for 3D Multi-Core Architectures

“…sources that are highly affected, directly and indirectly, by this rise in temperature. These sources would affect the reliability of 3D MPSoCs by accelerating the processor aging or the Mean-Time to Failure (MTTF) [23], which is the statistical average time for the MPSoC to breakdown permanently, as well as creating irreversible functional failures in the computation modules (e.g., storage) that limit the full utilization of these modules. In addition to the impacted reliability, high 3D MPSoC temperature would eventually lead to degraded performance by reducing the operating frequency due to increased propagation delays or reduced energy-efficiency resulted from the increased leakage power consumption.…”

“…Mean-Time To Failure [23,31]. The mean-time to failure would be heavily impacted due to the temperature impact on Time-Dependent Dielectric Breakdown (TDDB), Electromigration (EM), as well as stress migration and thermal cycling.…”