Reliability and Performance Analysis of FPGA-Based Fault Tolerant System

Noji, Ryoji; Fujie, Satoshi; Yoshikawa, Yasuhiro; Ichihara, Hideyuki; Inoue, Tomoo

doi:10.1109/dft.2009.27

Cited by 7 publications

(4 citation statements)

References 8 publications

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“…The stand-by-redundant system introduced in [16] is similar to the "k+m." The available set of CLBs are parti-tioned into p blocks, in whichm blocks are for spare and the rest are for application.…”

Section: Copyright C 2011 the Institute Of Electronics Information Amentioning

confidence: 99%

“…For the purpose of comparisons, several circuits from the ITC'99 benchmark were chosen to be implemented under the HPDP approach and the stand-by-redundant (SBR for short) approach. The SBR system introduced in [16] is an abstraction for FPGA-based FT systems. The "k+m" implementations introduced in [5], [10], [11], [14], [15] can also be formulated with the SBR model.…”

Section: Comparison With Stand-by-redundantmentioning

confidence: 99%

“…As in the SBR model,p denotes the number of available blocks in each tile (p was used in [16], to avoid confusion we change it top) andm denotes the number of spare blocks in each tile.…”

Section: Comparison With Stand-by-redundantmentioning

confidence: 99%

See 2 more Smart Citations

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

Zhou

et al. 2011

IEICE Trans. Fundamentals

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Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.

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Section: Copyright C 2011 the Institute Of Electronics Information Amentioning

confidence: 99%

Section: Comparison With Stand-by-redundantmentioning

confidence: 99%

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A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

Zhou

et al. 2011

IEICE Trans. Fundamentals

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“…For these purposes, the Markov dependability models can be used [15]. In [16], a mathematical Markov reliability model for SRAM-based FPGAs is presented.…”

Section: Introductionmentioning

confidence: 99%

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Kastil

Straka

Mičulka

et al. 2012

2012 15th Euromicro Conference on Digital System Design

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In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting soft errors into partial bitstream in FPGA by an SEU injector and the faults coverage of this architecture is obtained. From faults coverage, the failure rate and repair rate are evaluated. Then, for fault tolerant architecture Markov dependability models are created and how the reliability and availability parameters derived from this model for different configurations of architectures and faulty modules is demonstrated. The reliability analysis results are then shown.

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Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train

Galashi

Mohammadi

Gosheblagh

2014

J. Electron.(China)

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Reliability and Performance Analysis of FPGA-Based Fault Tolerant System

Cited by 7 publications

References 8 publications

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

A Domain Partition Model Approach to the Online Fault Recovery of FPGA-Based Reconfigurable Systems

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA

Hybrid redundancy approach to increase the reliability of FPGA based speed controller core for high speed train

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