Reliability and failure analysis in power GaN-HEMTs: An overview

Abstract

ower GaN transistors have recently demonstrated to be excellent devices for application in power electronics. The high breakdown field and the superior mobility of the 2-dimensional electron gas allow to fabricate transistors with low resistive and switching losses, that permit to increase the efficiency of switching mode power converters beyond 99 %. GaN-based transistors are currently supposed to be adopted in KW-range power converters; 650 V transistors are already available on the market, and 1200 V devices are currently under development. During operation, GaN power transistors can reach critical conditions, especially in the off-state (with a high VDS, in excess of 650 V), during hard-switching (where high current and voltage can be simultaneously present), and for high positive gate voltages (in the case of normally-off devices). This paper reports our most recent results on the gradual and catastrophic degradation of GaN-based power HEMTs. We present the results of three different case studies, on: (i) the time-dependent breakdown of power HEMTs submitted to high off-state stress; (ii) the degradation of HEMTs with p-GaN gate submitted to high gate stress; (iii) the hot electron effects in GaN-MISHEMTs submitted to high-Temperature source current stres

Drift Effects and Trap Analysis of Power-GaN-HEMT Under Switching Power Cycling

“…Table 2. Drift effects in GaN HEMTs, physical origin and measurement to test each effect, based in [8].…”

Gate dielectric reliability and instability in GaN metal-insulator-semiconductor high-electron-mobility transistors for power electronics

“…To solve this, a MIS-HEMT is often put in a cascode configuration with a silicon MOSFET. 27,28 During switching operation, in the OFF state (with V GS , V T ), the MIS-HEMT must be able to block a high voltage applied to the drain. [29][30][31] This is the state of greatest concern as it comes to TDDB.…”

“…The ON-state is more benign since 0 V is applied to the gate, and the drain is under a small bias. 28 The cascode configuration is designed such that the GaN devices are never subjected to a positive gate bias. However, the positive gate stress condition yields a relatively uniform electric field across the gate dielectric, as illustrated by the top image of Fig.…”

Impact of Sidewall Etching on the Dynamic Performance of GaN-on-Si E-Mode Transistors

“…Depletion-mode transistors have excellent performance, owing to the inherent high sheet carrier density at AlGaN/GaN hetero-interface caused by the material's unique polarization-induced electric field; on the other hand, obtaining enhancement-mode has been relatively difficult, and several optimization steps are still underway [3][4][5][6]. In order to obtain an enhancement mode device, a p-type doped GaN cap layer is introduced under the gate metal.…”