Reliability and analytical evaluations of no-clean flip-chip assembly

Clementi, J.; Dearing, G.O.; Zimmerman, Jonathan A.; Bergeron, C.

doi:10.1109/ectc.1995.517841

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…C4 attaclunent is very robust because of its self centering aligmnent capability. The tension force molten solder aligns the cltip on substrate pads and compensates for any cltip to substrate misaligmnent incurred during cltip placement [4].…”

Section: Introductionmentioning

confidence: 99%

Implementation of novel reflow profile of no-clean fluxes to enhance flux stability and oxide layer removal of the high lead solder bump

Amin

Cheah

et al. 2008

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)

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Various retlow profiles have been applied on different no-clean tluxes amount in removing the oxide layer of high lead solder blUnp. TIle wafers exposed to open air induce an oxide layer on the high lead solder bump. TItis oxide layer eventually creates the non wet phenomena in tlip cltip packaging. An experimental study is carried out by varying different soak time of the retlow profile to optimize the effectiveness of the flux in solving the eutectic and controlled collapse cltip connection (C4) high lead bump issue. wltich indirectly solves the non wet issue. Visual inspection on ltigh lead solder bump under ltigh power microscope is carried out after retlow process. Die pull test is carried out on the solder joint strength analysis to test the solder bump strength. Besides. experiments on substrate cleanliness test nonwet phenomena and die misaligmnent are also conducted with useful ltints to be implemented.

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Section: Introductionmentioning

confidence: 99%