Reliability analyses on a TSV structure for CMOS image sensor

Lwo, Ben-Je; Ni, Chung-Yen

doi:10.1109/ectc.2012.6248809

Cited by 3 publications

(2 citation statements)

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“…Note that the factors are 1 if not effected by the speciaifc environmental conditions in the list. The failure analyses After OM/SEM inspections, oxidation, delamination and flanking have been observed in the previous works for nonbiasing samples [6], and similar results were also found for the biasing samples (not shown). In addition, voids as shown in Figure 11 due to EM (electromigration) were found at the …”

Section: The Weibull Analysessupporting

confidence: 87%

“…Based on our earlier works on TSV property analyses [4][5] and the first reliability study on a TSV structure [6], an advanced study on TSV reliability under several different environmental variables was proposed and performed in this paper. To this end, a typical TSV structure for CIS (CMOS Imaging Sensor) applications was first designed and made.…”

Section: Introductionmentioning

confidence: 99%

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TSV reliability model under various stress tests

Lwo¹,

Frank

Lin

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Through Silicon Via (TSV) is the key technology for the 2.5D and 3D packaging, but reliability evaluations on the new technology products are limited because of the complexity of the environmental issues. To this end, reliability experiments on self-design TSV samples under combinations of several different environmental variables were proposed and performed in this study. The Weibull distribution model was next employed for reliability analyses and the parameters for each of the experimental results were extracted. After analyzing the Weibull parameters, factors that accelerate TSV unreliability are compared with discussions. This paper finally presents failure analyses through OM/SEM observations IntroductionDue to the advantages such as higher density, faster signal transmission, lower power consumption, broader functionality, and the abilities on heterogeneous connections, 2.5D and 3D packaging integration with TSV (Through Silicon Via) technology have drawn the attention of the packaging industry in the past decade, and the TSV applications were fast expanding at the same time. As the maturity of the TSV manufacturing process and the diverseness of possible TSV application, reliability evaluations on the newly developed technology products were rapidly introduced in the literature in recent years [1-3]. However, because of the complexity from many different environmental effects, the published TSV reliability data are still limited so that further related studies are needed.Based on our earlier works on TSV property analyses [4][5] and the first reliability study on a TSV structure [6], an advanced study on TSV reliability under several different environmental variables was proposed and performed in this paper. To this end, a typical TSV structure for CIS (CMOS Imaging Sensor) applications was first designed and made. To eliminate the parasitic resistance from the interconnecting wires and the contact resistance from the probing, four-point probe (4PP) measurements were employed for more accurate resistance measurements.After sample preparations, stress tests with different variables were performed. That is, the TSV samples were tested under several different environmental test conditions which were combinations of current bias, thermal aging, temperature cycling, and thermal-humidity cycling according to the JEDEC/JEP standards, and the failure criterion is set as

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Section: The Weibull Analysessupporting

confidence: 87%