Relevance of Gate Current for the Functionality of Deep Submicron CMOS Circuits

Schwantes, S.; Krautschneider, Wolfgang H.

doi:10.1109/essderc.2001.195303

Cited by 11 publications

(3 citation statements)

References 4 publications

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“…On the contrary of high permittivity gate dielectric, the pure gate oxide cannot be scaled with gate length for stand-by gate current consideration [1]. Therefore, retrograde profiles with epitaxial undoped Si growth [2] or with heavy ion [3] have been proposed to minimize SCE.…”

Section: Introductionmentioning

confidence: 99%

Channel Engineering Study for 50 nm P-Channel MOSFET

Guégan

Souil²,

Deleonibus³

et al. 2002

32nd European Solid-State Device Research Conference

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This paper discusses the optimisation of low cost 50 nm physical gate pMOSFET devices focusing on channel engineering. An extensive comparison of 50 nm pMOSFETs processed with either conventional or with retrograde channel profiles is presented. Except for Arsenic channel implants and annealing, the other pMOSFET design parameters such as gate oxide (2.2nm), pre-doped polysilicon gate with Boron, gate patterning with hybrid lithography, LDD, pocket architecture with nitride spacers and HDD implants with BF 2 , are similar. Gate lengths down to 45 nm have been processed. Furthermore, the impacts of annealing conditions ( RTA or spike ) are investigated. It is demonstrated that retrograde channel provides lower gate length sensitivity and wider process window with a drive current of 390 µA/µm at a specified Ioff of 70nA/µm despite thick gate oxide.

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Section: Introductionmentioning

confidence: 99%

Channel Engineering Study for 50 nm P-Channel MOSFET

Guégan

Souil²,

Deleonibus³

et al. 2002

32nd European Solid-State Device Research Conference

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“…However, I gate has been growing at a much faster rate and to this point has almost solely received attention from device engineers and not circuit designers and EDA tool developers. In [5] and [6], the authors examined the impact of gate leakage on circuit functionality but did not address its contribution to leakage power. In [7], the authors contribute the first circuit design concepts to reducing the impact of gate leakage -these focus on leveraging the lower I gate in PMOS devices by using p-type domino circuits rather than n-type.…”

Section: Introductionmentioning

confidence: 99%

Analysis and minimization techniques for total leakage considering gate oxide leakage

Lee

Kwong

Blaauw

et al. 2003

Proceedings of the 40th Annual Design Automation Conference

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In this paper we address the growing issue of gate oxide leakage current (I gate ) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I gate and subthreshold leakage (I sub ). The interaction between I sub and I gate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of I gate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I gate due to the dependence of gate leakage on stack node voltages.

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“…Many works are reported on the estimation of leakage current [4][5][6][7][8], but they only focus on subthreshold leakage. In [9,10], the authors examined the impact of gate leakage on functionality of circuit but did not address its contribution to leakage power. D. Lee [11,12] analyzes the mechanics of gate oxide leakage.…”

Section: Introductionmentioning

confidence: 99%

A maximum total leakage current estimation method

Xu¹,

Luo²,

Li³

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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As transistor size continues to scale down, leakage power has become a critical issue of integrated circuit design. The maximum total leakage current, which is mainly determined by the sum of subthreshold, gate and reverse biased junction BTBT leakage current, is an important parameter to guide low-leakage and high-performance circuit designs. Up to now, how to estimate the maximum leakage current accurately within endurable time remains unsolved. Precise simulators can calculate leakage current accurately, but are only practical for small circuits. In this paper, a fast maximum leakage current estimation method is introduced accompanied with our gate-level leakage current simulator called iLeakage. Experiments on ISCAS circuit suits show that the simulator is significantly accelerated under acceptable error compared with HSPICE and the algorithm is applicable for large circuits.

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Relevance of Gate Current for the Functionality of Deep Submicron CMOS Circuits

Cited by 11 publications

References 4 publications

Channel Engineering Study for 50 nm P-Channel MOSFET

Channel Engineering Study for 50 nm P-Channel MOSFET

Analysis and minimization techniques for total leakage considering gate oxide leakage

A maximum total leakage current estimation method

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