Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms

Abstract

The main memory in today's systems is based on DRAMs, which may offer low cost and high density storage for large amounts of data but it comes with a main drawback; DRAM cells need to be refreshed frequently for retaining the stored data. The refresh rate in modern DRAMs is set based on the worst-case retention time without considering access statistics, thereby resulting in very frequent refresh operations. Such high refresh rate leads eventually to large power and performance overheads, which are increasing with higher DRAM densities. However, such high refresh rates may not even required due to extremely low probability of the actual occurrence of the assumed worst-case scenarios, or due to the implicit refresh operation that occur during every memory access, a feature that has not been yet been studied in depth. In this paper, we enhance the state-of-the-art by systematically exploiting the implicit refresh of memory access for relaxing the refresh rate, while minimizing the resulting memory errors. This is achieved by modifying the algorithmic parameters that influence the access patterns such that all stored data are being touched within a target time interval that is necessary for meeting a target error rate. The proposed method is applied to stencil-based algorithms which represent a wide class of algorithms used in numerical analysis, image processing and cellular automata applications. The efficacy of the proposed method is demonstrated on an off-the-shelf server running a fully fledged Linux OS and results show that it is even possible to completely disable DRAM refresh with minor quality loss.

The Colored Refresh Server for DRAM

“…We evaluate our approach via hardware simulation, but software refresh control has been demonstrated on different hardware platforms [3], and CRS could be implemented with similar software refresh controls on such platforms (with some engineering overhead). DRAM refreshes are synchronous with the processor clock (if the clock is fixed) and can, in fact, optionally be disabled for a subset of ranks on contemporary single-and multi-core systems [28]. Furthermore, the phase when a per-rank hardware refresh starts could be reverse engineered by monitoring access latencies during the initialization of a CRS-controlled system on these platforms.…”

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

“…Once we applied such a method to the popular Stencil algorithms, we observed that access intervals are shorter than the refresh period [12], indicating that such technique can be further exploited for limiting the manifested DRAM errors and reduce the reliance on ECC and required error corrections.…”

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

“…location and number, on separate DIMM sets. For example, nw(8) and srad (8) trigger errors only on the second DIMM set, which can be attributed to manufacturing process variations. Meanwhile, the graph-analytics benchmark has the highest P DEL, the highest total number of reported errors and the highest F F W among all benchmarks on both DIMM sets, which implies a certain dependence between a running application and the DRAM error behaviour.…”

“…Many studies tried to address this reality by reducing the refresh power, estimated to incur 40 % overhead in future 64Gb densities due to the conservative selection of the refresh period needed for addressing the limited retention time of the DRAM cells [3]. The majority of the proposed schemes rely on offline identification of the weak cells using few known data patterns and the adoption of different refresh periods for various cells, rows and pages [3], [4], [5], [6], [7], [8]. However, recent studies have proven such schemes ineffective, since they revealed that the cell retention time varies dynamically due to data-dependent circuit level crosstalk effects [3], [9].…”