Reinventing EDA with manycore processors

Sapatnekar, Sachin S.; Haritan, Eshel; Keutzer, Kurt; Devgan, Anirudh; Kirkpatrick, Desmond A.; Meier, S.R.; Pryor, Duaine; Spyrou, Tom

doi:10.1145/1391469.1391502

Cited by 8 publications

(5 citation statements)

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“…In multithreading, each program divides between many threads and could be run concurrently. Speedup of multi-thread programs is improved considerably in recent years by emerging multi core processors with high bandwidth channels to the sheared memory [3]. VLSI CAD algorithms are very time-consuming algorithms with non-polynomial time complexity.…”

Section: Parallel Vlsi-cad Algorithmsmentioning

confidence: 99%

“…Exponential enlargement of modern circuits is an important challenge for CAD tools because the speed of them should be increased dramatically to cope with hardware complexity growth [2,3]. This gap (i.e.…”

Section: Introductionmentioning

confidence: 99%

“…In floorplanning phase, location and shape for large block of the design are determined and exact location and orientation of the standard cells is fixed in placement step and finally, the geometry of interconnects are details in routing stage. A bundle of algorithms are used in these steps that most of them are NP-complete and NP-hard algorithms [2,3]. Routing is the most sophisticated and time-consume part of physical design.…”

Section: Introductionmentioning

confidence: 99%

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Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

Farkish

Jahanian

2011

IEICE Electron. Express

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Abstract:VLSI physical design algorithms are generally nonpolynomial algorithms with very long runtime. In this paper, we parallelize the Pathfinder global routing algorithm -a widely used FPGA routing algorithm-for running on multi-core systems to improve runtime of routing process. Our experimental results show that the runtime of proposed multi-threaded global routing reduces by 47.8% and 70.9% (on average) with 2 and 4 concurrent threads, respectively on a quad-core processor without any quality degradation.

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Section: Parallel Vlsi-cad Algorithmsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

Farkish

Jahanian

2011

IEICE Electron. Express

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show abstract

“…This exponential growth of modern circuits is an important challenge for computer-aided design tools because their runtime will be increased dramatically coping with this complexity growth [3], [4]. On the other hand, the gap between complexity growth and productivity of CAD tools (i.e.…”

Section: Introductionmentioning

confidence: 99%

Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform

Taheri¹,

Jahanian²,

Molaie³

2017

IJCTE

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Abstract-Significant portion of digital design flow runtime is related to the physical design stages. Partitioning is a critical stage of physical design and its quality and runtime has considerable impact on physical design efficiency. In this paper, a new parallel partitioning algorithm is proposed and it is suitable for GPU system. In the proposed algorithm, coarsening phase of the partitioning is accelerated by parallelizing on GPU. Experimental results show that runtime can be improved up to 7x for attempted circuit with negligible quality degradation.Index Terms-GPU programming, multilevel partitioning, parallel algorithms, physical design.

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“…Although there has been tremendous evolution in shifting traditional sequential Electronic Design Automation (EDA) tools into their parallel implementations for modern multicore computers in the past decade [3,4,5,6,7,8,9,10,11], the future multicore computing will apparently be hindered by the dramatically-increased chip power consumption and slowly-improved heat sinking capability. As a result, present-day computer architects and research community are forced to seek alternative paradigms to sustain ever-increasing performance.…”

Section: Chapter 1 Introductionmentioning

confidence: 99%

Scalable Integrated Circuit Simulation Algorithms for Energy-Efficient Teraflop Heterogeneous Parallel Computing Platforms

Han

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Reinventing EDA with manycore processors

Cited by 8 publications

References 0 publications

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

Parallelizing the FPGA global routing algorithm on multi-core systems without quality degradation

Parallelizing the Coarsening Phase of Hyper-Edge Partitioning on the GPU Platform

Scalable Integrated Circuit Simulation Algorithms for Energy-Efficient Teraflop Heterogeneous Parallel Computing Platforms

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