Register Transformations with Multiple Clock Domains

Albrecht, Alvin R.; Hu, Alan J.

doi:10.1007/3-540-44798-9_11

Cited by 4 publications

(2 citation statements)

References 18 publications

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“…Previously proposed solutions have been largely piece-wise, such as translating clocked LTL properties [13] that can be handled by a standard BMC solver, reducing the verification model size by using phase abstraction techniques [14][15][16][17], and generating a clocking scheme from given frequency constraints based on event queue semantics to avoid unnecessary unrolling during BMC [18].…”

Section: A Motivationmentioning

confidence: 99%

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Ganai

Gupta

2007

2007 Asia and South Pacific Design Automation Conference

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Current industry trends in system design -multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, and level-sensitive latches, combined with clocked -pose additional challenges to verification efforts. We propose an integrated solution that improves SAT-based Bounded Model Checking (BMC) by orders of magnitude, for verification of synchronous multi-clock systems with clocked LTL properties. Our main contributions are: a) Efficient clock modeling schemes to handle clock related challenges uniformly, b) Generation of automatic schedules and clock constraints to avoid unnecessary unrolling and loop-checks in BMC, c) Dynamic simplification of BMC problem instances with clock constraints, and d) Customized BMC translations-with incremental formulations and learning-to directly handle PSL-style clocked specifications. We demonstrate the effectiveness of our approach on some OpenCores multi-clock system benchmarks. I IntroductionA continuing push for high performance and low power designs has greatly increased the system design complexity. One norm of today's System-on-Chip (SoC) design is the use of multiple clocks and phases, and gated clocks. This paradigm shift from a single global clock synchronous design paradigm was inevitable, as distributing a single clock across the increasing size of die, number of latches, frequencies of clocks and delays of wires poses a major bottleneck in achieving the goals of higher performance and lower power [1]. For power-conscious designs, designers often use gated clocks to reduce or disable the switching activity of certain portions of the design. Furthermore, SoC designs comprise several intellectual property (IP) blocks that operate at different clock frequencies and need to communicate across asynchronous clock domains. Each of these design styles increases the verification complexity in terms of increased number of state bits and deeper bug traces.Formal verification techniques like SAT-based Bounded Model Checking (BMC) [2-5] due to several advancements -improved DPLL-style SAT solvers [6], on-the-fly circuit simplification [7,8], partitioning and incremental BMC formulation [9], and SAT-based incremental learning [8, 10, 11] -have been gaining wide acceptance as a scalable solution compared to BDD-based symbolic model checking [12]. The performance of SAT-based BMC is less sensitive to the number of flip-flops (FFs) and does not suffer from space explosion. A. MotivationAn integrated solution to verify multi-clock systems comprising multiple clocks, clocks with arbitrary frequency ratios, multi-phased clocks, gated clocks, level-sensitive latches, combined with clocked specification, that exploits recent advancements in SAT-based BMC has been lacking. Previously proposed solutions have been largely piece-wise, such as translating clocked LTL properties [13] that can be handled by a standard BMC solver, reducing the verification model size by using phase abstraction techniques [14][15][16][17], and generating a clocking scheme from given fr...

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Section: A Motivationmentioning

confidence: 99%

Efficient BMC for Multi-Clock Systems with Clocked Specifications

Ganai

Gupta

2007

2007 Asia and South Pacific Design Automation Conference

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“…In [14], Albrecht and Hu presents a theory for reasoning about register transformations in the presence of multiple clock domains. Strict phase abstraction is one of a number of particular transformation rules that can be derived in this theory.…”

Section: Related Workmentioning

confidence: 99%

Automatic generalized phase abstraction for formal verification

Bjesse

Kukula

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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Abstract-A standard approach to improving circuit performance is to use an N -phase design style where combinational logic is interspersed freely between level sensitive latches controlled by separate clocks. Unfortunately, the use of an N -phase design style will increase the number of state variables by a factor of N , making formal verification many orders of magnitude harder. Previous approaches to solving this problem restrict the kind of designs that can be handled severely and construct an abstracted netlist with fewer state variables by a syntactic analysis that requires the user to identify clocks. We extend the current state of the art by introducing a phase abstraction algorithm that (1) poses no restrictions on the design style that can be used, that (2) avoids an error prone syntactic analysis, that (3) requires no input from users, and that (4) can be integrated into any model checker without requiring HDL code analysis.

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