Register tiling in nonrectangular iteration spaces

Abstract

Loop tiling is a well-known loop transformation generally used to expose coarse-grain parallelism and to exploit data reuse at the cache level. Tiling can also be used to exploit data reuse at the register level and to improve a program's ILP. However, previous proposals in the literature (as well as commercial compilers) are only able to perform multidimensional tiling for the register level when the iteration space is rectangular. In this article we present a new general algorithm to perform multidimensional tiling for the register level in both rectangular and nonrectangular iteration spaces. We also propose a simple heuristic to determine the tiling parameters at this level. Finally, we evaluate our method using as benchmarks typical linear algebra algorithms having nonrectangular iteration spaces and compare our proposal against hand-optimized vendor-supplied numerical libraries and against commercial compilers able to perform optimizing code transformations such as inner unrolling, unroll-and-jam, and software pipelining. Measurements were taken on three different superscalar microprocessors. Results will show that our method outperforms the native compilers (showing speedups of 2.5 in average) and matches the performance of vendor-supplied numerical libraries. The general conclusion is that compiler technology can make it possible for nonrectangular loop nests to achieve as high performance as hand-optimized codes.

Architecture-aware classical Taylor shift by 1

“…We perform only additions; signed digits will implicitly distinguish between addition and subtraction. The technique we use is an instance of register tilinga computation method that groups the operands, loads them into machine registers, and operates on the operands without referencing the memory [2,14]. We call our method tile method.…”

“…The introduction of signed digits, suspended normalization, radix reduction, and delayed carry propagation enables our algorithm to take advantage of the technique of register tiling which is commonly used by optimizing compilers [2,14]. While our algorithm is written in a high-level language, it depends on several parameters that can be tuned to the underlying architecture.…”

A Survey of Loop Parallelization: Models, Approaches, and Recent Developments

“…The proposed method can process imperfect loops and even use the feedback information at run time to tune related parameters. Fine grained tiling can obtain more parallelism, such as Jimenez et al [32] proposed a multidimensional tiling approach, which includes four phases: 1) iteration space tiling, 2) index set splitting, 3) unrolling phase, 4) scalar replacement. Among them, scalar replacement is to remove unnecessary load and store operations, which realizes the optimization of registers.…”

Buffer and Register Allocation for Memory Space Optimization

“…In our previous work [2,3], we have presented a method of array reallocation by buffers which reduces significantly the number of cache misses. In this paper, we combine this method with register allocation [15,16]. To achieve this goal, we initially compute for each array the memory volume of live data and then replace that array by one or several buffers.…”