Register allocation for irregular architectures

Scholz, Bernhard; Eckstein, Erik

doi:10.1145/513852.513854

Cited by 12 publications

(28 citation statements)

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“…The third register allocator is based on partitioned Boolean quadratic programming (PBQP) [35]. The algorithm runs in worstcase exponential time and does optimal spilling with respect to a set of Boolean constraints generated from the program text.…”

Section: Resultsmentioning

confidence: 99%

“…For SPEC CPU2000, the compilation time of our implementation is as fast as that of the extended version of linear scan used by LLVM, which is the JIT compiler in the openGL stack of Mac OS 10.5. Our implementation produces x86 code that is of similar quality to the code produced by the slower, state-of-the-art iterated register coalescing of George and Appel with the extensions proposed by Smith, Ramsey, and Holloway in 2004.Researchers and compiler writers have used a variety of abstractions to model register allocation, including graph coloring [12,17,36], integer linear programming [2,19], partitioned Boolean quadratic optimization [21,35], and multi-commodity network flow [25]. These abstractions represent different tradeoffs between compilation speed and quality of the produced code.…”

mentioning

confidence: 99%

“…Researchers and compiler writers have used a variety of abstractions to model register allocation, including graph coloring [12,17,36], integer linear programming [2,19], partitioned Boolean quadratic optimization [21,35], and multi-commodity network flow [25]. These abstractions represent different tradeoffs between compilation speed and quality of the produced code.…”

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Register allocation by puzzle solving

Pereira

Palsberg

2008

SIGPLAN Not.

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We show that register allocation can be viewed as solving a collection of puzzles. We model the register file as a puzzle board and the program variables as puzzle pieces; pre-coloring and register aliasing fit in naturally. For architectures such as PowerPC, x86, and StrongARM, we can solve the puzzles in polynomial time, and we have augmented the puzzle solver with a simple heuristic for spilling. For SPEC CPU2000, the compilation time of our implementation is as fast as that of the extended version of linear scan used by LLVM, which is the JIT compiler in the openGL stack of Mac OS 10.5. Our implementation produces x86 code that is of similar quality to the code produced by the slower, state-of-the-art iterated register coalescing of George and Appel with the extensions proposed by Smith, Ramsey, and Holloway in 2004.Researchers and compiler writers have used a variety of abstractions to model register allocation, including graph coloring [12,17,36], integer linear programming [2,19], partitioned Boolean quadratic optimization [21,35], and multi-commodity network flow [25]. These abstractions represent different tradeoffs between compilation speed and quality of the produced code. For example, linear scan [33, 38] is a simple algorithm based on the coloring of interval graphs that produces code of reasonable quality with fast compilation time; iterated register coalescing [17] is a more complicated algorithm that, although slower, tends to produce code of better quality than linear scan. Finally, the Appel-George algorithm [2] achieves optimal spilling, with respect to a cost model, in worst-case exponential time via integer linear programming.In this paper we introduce a new abstraction: register allocation by puzzle solving. We model the register file as a puzzle board and the program variables as puzzle pieces. The result is a collection of puzzles with one puzzle per instruction in the intermediate representation of the source program. We will show that puzzles are Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. easy to use, that we can solve them efficiently, and that they produce code that is competitive with the code produced by state-ofthe-art algorithms. Specifically, we will show how for architectures such as PowerPC, x86, and StrongARM we can solve each puzzle in linear time in the number of registers, how we can extend the puzzle solver with a simple heuristic for spilling, and how precoloring and register aliasing fit in naturally. Pre-colored variables are variables that have been assigned to particular registers before register allocation begins; two register names alias [36] when an assignment to one register name can affect the value of ...

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Section: Resultsmentioning

confidence: 99%

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Register allocation by puzzle solving

Pereira

Palsberg

2008

SIGPLAN Not.

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“…A number of researchers have cast register allocation as a mathematical-programming problem, rather than a graph-coloring problem [Goodwin and Wilken 1996;Kong and Wilken 1998;Appel and George 2001;Fu and Wilken 2002;Scholz and Eckstein 2002;Hirnschrott, Krall, and Scholz 2003]. These approaches can handle a wide variety of architectural irregularities, but these benefits come at the cost of significant increases in compile time.…”

Section: Related Workmentioning

confidence: 99%

A generalized algorithm for graph-coloring register allocation

Smith

Ramsey

Holloway

2004

Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation

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Graph-coloring register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single register name may appear in multiple register classes, where a class is a set of register names that are interchangeable in a particular role. Second, multiple register names may be aliases for a single hardware register. We present a generalization of graph-coloring register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the register classes and a map of the register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

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“…However ILP is NP-hard, and the ILP-based approaches tend to have far worse runtime compared to graph coloring. There are also approaches modeling register allocation as a partitioned boolean quadratic programming (PBQP) problem [30,22]. They can handle some irregularities in the architecture in a more natural way than older graph-coloring approaches, but do not handle coalescing and other interactions that can arise out of irregularities in the instruction set.…”

Section: Introductionmentioning

confidence: 99%

Optimal Register Allocation in Polynomial Time

Krause

2013

Lecture Notes in Computer Science

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A graph-coloring register allocator that optimally allocates registers for structured programs in polynomial time is presented. It can handle register aliasing. The assignment of registers is optimal with respect to spill and rematerialization costs, register preferences and coalescing. The register allocator is not restricted to programs in SSA form or chordal interference graphs. It assumes the number of registers is to be fixed and requires the input program to be structured, which is automatically true for many programming languages and for others, such as C, is equivalent to a bound on the number of goto labels per function. Non-structured programs can be handled at the cost of either a loss of optimality or an increase in runtime. This is the first optimal approach that has polynomial runtime and works for such a huge class of programs.An implementation is already the default register allocator in most backends of a mainstream cross-compiler for embedded systems.

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Register allocation for irregular architectures

Cited by 12 publications

References 0 publications

Register allocation by puzzle solving

Register allocation by puzzle solving

A generalized algorithm for graph-coloring register allocation

Optimal Register Allocation in Polynomial Time

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