Register allocation and instruction scheduling in Unison

Lozano, Roberto Castañeda; Carlsson, Mats; Blindell, Gabriel Hjort; Schulte, Christian

doi:10.1145/2892208.2892237

Cited by 8 publications

(7 citation statements)

References 2 publications

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“…We will explore in detail how this paper's model can be integrated with a constraint model for register allocation and instruction scheduling introduced in [10,11].…”

Section: Discussionmentioning

confidence: 99%

“…Consequently, the number of selected matches may be higher than necessary. This problem is similar to spilling reused temporaries in [11] and can be addressed by adapting the idea of alternative temporaries introduced in [10].…”

Section: A Constraint Model For Universal Instruction Selectionmentioning

confidence: 99%

“…Crucially, instruction selection with a universal representation is only feasible with an approach as expressive as a constraint model. Second, the paper's approach will be essential to integrate instruction selection with register allocation and instruction scheduling as the other code generation tasks that we have explored in previous work [11,10]. It is only the combination of all three interdependent tasks that will enable generating optimal code for modern processors.…”

Section: Introductionmentioning

confidence: 99%

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Modeling Universal Instruction Selection

Blindell

Lozano

Carlsson

et al. 2015

Lecture Notes in Computer Science

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Abstract. Instruction selection implements a program under compilation by selecting processor instructions and has tremendous impact on the performance of the code generated by a compiler. This paper introduces a graph-based universal representation that unifies data and control flow for both programs and processor instructions. The representation is the essential prerequisite for a constraint model for instruction selection introduced in this paper. The model is demonstrated to be expressive in that it supports many processor features that are out of reach of state-of-the-art approaches, such as advanced branching instructions, multiple register banks, and SIMD instructions. The resulting model can be solved for small to medium size input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their expressiveness and their potential to be combined with models for other code generation tasks.

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“…We will explore in detail how this paper's model can be integrated with a constraint model for register allocation and instruction scheduling introduced in [10,11].…”

Section: Discussionmentioning

confidence: 99%

Section: A Constraint Model For Universal Instruction Selectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modeling Universal Instruction Selection

Blindell

Lozano

Carlsson

et al. 2015

Lecture Notes in Computer Science

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“…In [39] and [40], data reuse is taken into account either by greedily assigning the available registers to the data array references or by applying loop unroll transformation to expose reuse and opportunities for maximizing parallelism. In [41], a survey on combinatorial register allocation and instruction scheduling is given. Finally, regarding data cache miss elimination methods, much research has been done in [42] …”

Section: Related Workmentioning

confidence: 99%

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

Kelefouras

2017

Computing

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Today's compilers have a plethora of optimizations-transformations to choose from, and the correct choice, order as well parameters of transformations have a significant/large impact on performance; choosing the correct order and parameters of optimizations has been a long standing problem in compilation research, which until now remains unsolved; the separate subproblems optimization gives a different schedule/binary for each sub-problem and these schedules cannot coexist, as by refining one degrades the other. Researchers try to solve this problem by using iterative compilation techniques but the search space is so big that it cannot be searched even by using modern supercomputers. Moreover, compiler transformations do not take into account the hardware architecture details and data reuse in an efficient way.In this paper, a new iterative compilation methodology is presented which reduces the search space of six compiler transformations by addressing the above problems; the search space is reduced by many orders of magnitude and thus an efficient solution is now capable to be found. The transformations are the following: loop tiling (including the number of the levels of tiling), loop unroll, register allocation, scalar replacement, loop interchange and data array layouts. The search space is reduced a) by addressing the aforementioned transformations together as one problem and not separately, b) by taking into account the custom hardware architecture details (e.g., cache size and associativity) and algorithm characteristics (e.g., data reuse).The proposed methodology has been evaluated over iterative compilation and gcc/icc compilers, on both embedded and general purpose processors; it achieves significant performance gains at many orders of magnitude lower compilation time.

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“…Second, auxiliary constraints can easily be added to the already existing model, enabling code generation for complicated target machines as well as extending the instruction support to include interdependent instructions. Third, recent advancements in solver technology have made these kinds of techniques viable options for practical use (this is for example showcased by Castañeda Lozano et al [65,66]). However, current implementations are still orders-of-magnitude slower than their heuristic counterparts and are thus in need of further research.…”

Section: Future Challengesmentioning

confidence: 99%

Instruction Selection

Blindell

2016

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Register allocation and instruction scheduling in Unison

Cited by 8 publications

References 2 publications

Modeling Universal Instruction Selection

Modeling Universal Instruction Selection

A methodology pruning the search space of six compiler transformations by addressing them together as one problem and by exploiting the hardware architecture details

Instruction Selection

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