Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar, Srimat; Rothweiler, S.G.; Agrawal, Vishwani D.

doi:10.1109/vtest.1995.512611

Cited by 8 publications

(6 citation statements)

References 23 publications

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“…The drawbacks of the well-known algorithms of PO-DEM [17] and FAN [16] for circuits with tristate devices have been well reported in the literature [12,26,27,31,34,37]. Since tristate devices can float, most of these algorithms use a new logic value (Z ) to denote an output different from the traditional binary values of 0 and 1.…”

Section: Previous Workmentioning

confidence: 99%

“…High performance circuits usually include pass transistor logic, domino and exor/exnor trees [33] that are commonly modeled with tristate elements. While tristate models are acceptable for design verification, ATPG tools are often unable to generate patterns for faults in such circuits, and exhibit low fault coverage, primarily due to the propagation of Bose unknown (X) values [12,31]. While 2-pattern tests can be used to test certain faults in tristate logic [37], single pattern tests are sufficient for combinational logic designed with pass transistors (Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Past approaches to this problem have required additional analysis during the ATPG phase [12,31,[35][36][37], with minimal changes to the model generation step during the design phase. While some of these algorithms involve new ATPG algorithms [12], others require design knowledge that is often not available to the test designer and are not easy to automate [31,37].…”

Section: Introductionmentioning

confidence: 99%

“…While some of these algorithms involve new ATPG algorithms [12], others require design knowledge that is often not available to the test designer and are not easy to automate [31,37]. Examples include buses that can never drive conflicting values to the bus node due to complete decoding of the bus control logic.…”

Section: Introductionmentioning

confidence: 99%

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Modeling Custom Digital Circuits for Test

Bose

2004

J Electron Test

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Models meant for logic verification and simulation are often used for Automatic Test Pattern Generation (ATPG). For custom digital circuits, these models contain many tristate devices that tend to lower coverage for stuckfaults. Additionally, these tristate devices contribute to increased ATPG runtimes, fewer generated test sequences, and an overall lower test quality. The circuit under test is partitioned into channel connected sub-networks (CCSN) that consist of transistors that are connected at their source or drain terminals, except when these terminals are power, ground or primary inputs. Unlike other published work, algorithms presented in this paper analyze each CCSN in the context of its environment, thereby capturing the logical relationships among its input signals. Other algorithms presented include identification and modeling of embedded latches, clock generators and memory circuits. An abstract array model for memory that reduces the size of the model and increases simulation speed is also presented. When one specific feature of the algorithm was disabled, experimental results showed higher ATPG runtimes of about 35%, and an average decrease in fault coverage of around 15-20%. For the largest data cache, the memory modeling algorithm decreased the number of primitives from 1.23 million to 139 thousand.

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Section: Previous Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Modeling Custom Digital Circuits for Test

Bose

2004

J Electron Test

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“…We also investigate the use of the proposed methodology for identifying and removing redundancies in production circuits. Some details of this work were presented at the 13th IEEE VLSI Test Symposium [14].…”

Section: Introductionmentioning

confidence: 99%

Redundancy removal and test generation for circuits with non-Boolean primitives

Chakradhar¹,

Rotherweiler²,

Agrawal³

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Production VLSI circuits typically consist of primitives like tristate buffers, bidirectional buffers, and bus configurations that assume non-Boolean values like the high-impedance state. We describe a systematic methodology for extending test generation algorithms that work on combinational circuits with only Boolean primitives to full-scan production circuits. Key features of the methodology are illustrated using the energy minimization based test generation algorithm for combinational circuits. The main features of our methodology that make the test generation algorithm practical for large production circuits are: 1) only one Boolean variable is used to represent the value on a signal and all signals assume only Boolean values during the test generation procedure; 2) the function of non-Boolean primitives is separated into Boolean and non-Boolean components with energy functions required only for the Boolean component; and 3) non-Boolean components are implicitly considered in the energy minimization procedure. In this process, no new energy functions other than the normal Boolean gate energy functions are needed. We give a method for identifying and removing redundancies in production circuits using energy minimization. The formulation is also applicable to Boolean satisfiability and BDD methods. We first use the test generation algorithm for identifying undetectable faults and then relax specific constraints in the original test generation problem by ignoring the non-Boolean components. We show that undetectability in the relaxed formulation implies redundancy. We report redundancy removal results for production VLSI circuits, ISCAS 85, and full-scan versions of the ISCAS 89 benchmark circuits.

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Combinational ATPG theorems for identifying untestable faults in sequential circuits

Agrawal

Chakradhar²

1995

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Redundancy removal and test generation for circuits with non-Boolean primitives

Cited by 8 publications

References 23 publications

Modeling Custom Digital Circuits for Test

Modeling Custom Digital Circuits for Test

Redundancy removal and test generation for circuits with non-Boolean primitives

Combinational ATPG theorems for identifying untestable faults in sequential circuits

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