Redundancy identification using transitive closure

Agrawal, Vishwani D.; Bushnell, M.L.; Qi, Lin

doi:10.1109/ats.1996.555127

Cited by 9 publications

(5 citation statements)

References 20 publications

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“…Agrawal and colleagues proposed a redundant-fault identification method based on simultaneous analysis of all signal values of the circuit [14], which could identify about the same number of redundant faults in about twice the time taken by FIRE. A method of improvement of implications is presented in Ref.…”

Section: Introductionmentioning

confidence: 99%

Identification of redundant faults in combinational circuits

Minamiyama

Takamatsu

2000

Syst. Comp. Jpn.

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An efficient redundant‐fault identification method is useful for test pattern generation. The authors earlier proposed a method for redundant fault identification of combinational circuits that consisted of the procedures regarding the fan‐out stems used in the FIRE algorithm [12, 13] and the analysis of target faults [17]. But it was shown that the method identifies more redundant faults than those found in FIRE, with a problem of long CPU times. In this paper, implications are extended in order to identify more redundant faults; and in order to accelerate the process, parallel operations are introduced into both the procedures of fan‐out stems and analysis of the target faults. Further, programs are developed for the proposed method and are applied to the benchmark circuits to verify the effectiveness of the method. The experimental results show the possibility of fast identification of larger numbers of redundant faults than in previous methods. © 2000 Scripta Technica, Syst Comp Jpn, 31(6): 65–73, 2000

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Section: Introductionmentioning

confidence: 99%

Identification of redundant faults in combinational circuits

Minamiyama

Takamatsu

2000

Syst. Comp. Jpn.

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“…In general, for an n-input gate we require n + 1 anding nodes, each having n incoming edges and one outgoing edge. Also for each input signal of the gate an implicit observability AND gate expresses the observability related implications [1,14]. For example, for signal a the observability is expressed as O a = bO c .…”

Section: Prior Workmentioning

confidence: 99%

“…The logical implications are expressed as edges. The binary relationships obtained from Equation 1 can be represented in the implication graph of directed edges as shown in Figure 1 [1,3,7]. An enhanced implication graph (EIG) was proposed by Henftling et al [18,37].…”

Section: Prior Workmentioning

confidence: 99%

“…Agrawal et al proposed a fault-independent redundancy identification technique using an implication graph and transitive closure that analyzes circuit topology and function without targeting a specific fault [1]. In their work, they define observability variables, O x , for every circuit line x.…”

Section: Introductionmentioning

confidence: 98%

“…These methods can find some redundancies very quickly [20] but are not exhaustive in terms of finding all redundant faults. Such methods can be further classified as testability analysis [2,16,17,30,35] or implication based techniques [1,10,11,14,20,28,29].…”

Section: Introductionmentioning

confidence: 99%

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Using contrapositive law in an implication graph

Dave¹,

Agrawal

Bushnell

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new "oring" node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used "anding" node. An n-input gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding node graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is a set of new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS'85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. The best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.

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Detection of Redundant Arcs in Entity Relationship Conceptual Models

Bowers

2003

Lecture Notes in Computer Science

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Redundancy identification using transitive closure

Cited by 9 publications

References 20 publications

Identification of redundant faults in combinational circuits

Identification of redundant faults in combinational circuits

Using contrapositive law in an implication graph

Detection of Redundant Arcs in Entity Relationship Conceptual Models

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