Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS

Ida, Jiro; Yoshimaru, Masaki; Usami, Teruo; Ohtomo, A.; Shimokawa, Kuniyasu; Kita, Akio; Ino, M.

doi:10.1109/vlsit.1994.324378

Cited by 19 publications

(3 citation statements)

References 1 publication

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“…Reduction in metal pitch however degrades interconnect RC delay which tends to curtail the benefits of interconnect scaling [1]. Low dielectric constant (Low-k) materials have been introduced [2] as an alternative intra-level insulator to reduce interconnect capacitance (therefore delay) and cross-talk noise to enhance circuit performance. Recently it has been demonstrated that thermal effects, instead of electromigration itself, will start to dominate interconnect design guidelines for advanced high performance interconnects [3,4].…”

Section: Introductionmentioning

confidence: 99%

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal

Banerjee

Amerasekera

Dixit

et al.

International Electron Devices Meeting. Technical Digest

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The effect of interconnect scaling and low-k dielectric on the thermal characteristics of interconnect structures has been characterized for the first time under DC and pulsed current conditions. It is shown that under DC conditions the thermal impedance of metal lines increases by about 10% when the low-k dielectric is used as the gap fill. The critical current density for the low-k structures under pulsed condition is shown to be about 10-30% lower than that of standard dielectric structures depending on metal and pulse widths.

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Section: Introductionmentioning

confidence: 99%

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal

Banerjee

Amerasekera

Dixit

et al.

International Electron Devices Meeting. Technical Digest

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“…Previous work has shown the benefits of incorporating fluorinated silicate glass ͑FSG, k ϭ 3.5-3.7) into BEOL applications, as opposed to using the conventional undoped silicate glass ͑USG, k ϭ 3.9-4.1). 10,13,14 Nevertheless, accommodating dielectrics with even lower k values is inevitable as Cu interconnects are further scaled down to the 0.15/0.13 m node. C-doped low-k CVD organosilicate glasses ͑OSGs͒ become feasible candidates because of their lower k values ͑Ͻ3.0͒ than that of FSG.…”

mentioning

confidence: 99%

Physical and Electrical Characteristics of Methylsilane- and Trimethylsilane-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

Shiung

Chiang

et al. 2001

J. Electrochem. Soc.

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This work investigates the physical and electrical properties of two species of inorganic C-doped low dielectric constant ͑low-k͒ chemical vapor deposited ͑CVD͒ organosilicate glasses ͑OSGs, ␣-SiCO:H͒. They are both deposited by plasma-enhanced CVD ͑PECVD͒ processes using methylsilane ͓͑CH 3 ͒SiH 3 , 1 MS͔-and trimethylsilane ͓͑CH 3 ͒ 3 SiH, 3 MS͔-based gases as the reagents, and are designated as OSG1 and OSG2, respectively. Experimental results indicate that the thermal stability temperature of OSG1 is 500°C, while that of OSG2 is 600°C, based on the results of thermal annealing for 30 min in an N 2 ambient. The deterioration of the low-k property in OSG1 is predominately due to the thermal decomposition at temperatures above 500°C of methyl (ϪCH 3) groups, which are introduced to lower the density and polarizability of OSGs. For the Cu-gated oxide-sandwiched low-k dielectric metal-insulator-semiconductor ͑MIS͒ capacitors, Cu permeation was observed in both OSG1 and OSG2 after the MIS capacitors were bias-temperature stressed at 150°C with an effective applied field of 0.8 MV/cm. Moreover, Cu appeared to drift more readily in OSG1 than in OSG2, presumably because OSG1 has a more porous and less cross-linked structure than OSG2. The Cu penetration can be mitigated by a thin nitride dielectric barrier.

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“…The scaling of ULSI leads to continuous increase in current density that results in ever greater interconnect Joule heating. In addition, a variety of low-k materials have been introduced to reduce the RC delay, dynamic power consumption and crosstalk noise in advanced technology [1,2]. Together with the poor thermal conductivity of such materials and more metal levels added, the increasing thermal impedance further exacerbates temperature rise in interconnects [3].…”

Section: Introductionmentioning

confidence: 99%

Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects

Chiang¹,

Banerjee²,

Saraswat³

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

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This paper presents both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low-k interconnects under steady-state and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as additional heat sinking paths to alleviate the temp erature rise in the metal wires, is included in our analysis to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used. The analytical model is then applied to estimate the temperature distribution in multi-level interconnects. In addition, we discuss the possibility that, under the impact of thermal effects, the performance improvement expected from the use of low-k dielectric materials may be degraded. Furthermore, thermal coupling between wires is evaluated and found to be significant. Finally, the impact of metal wire aspect ratio on interconnect thermal characteristics is discussed.

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Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS

Cited by 19 publications

References 1 publication

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal

The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal

Physical and Electrical Characteristics of Methylsilane- and Trimethylsilane-Doped Low Dielectric Constant Chemical Vapor Deposited Oxides

Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects

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