Reduction of Process Variations for Sub-5-nm Node Fin and Nanosheet FETs Using Novel Process Scheme

A Novel Investigation Method for the S21 Detection Circuit

“…The novel investigation method proposed by this research serves as an efficient and low-cost testing method for the S 21 detection circuit. As introduced in Section 1, related works in various domains [12][13][14][15][16][17][18][19][20][21][22][23][24] have provided valuable inspiration and knowledge for the development of the method. Because the investigation method is particularly designed for the S 21 detection circuit, counterparts highly comparable with the method seem to be absent in the literature.…”

“…Zahira [14] developed an efficient gate-sizing methodology for improving circuit speed in the presence of independent intra-die process variations. Yoon [15] revealed that the performance of sub-5-nm NSFETs is less affected by process variations than that of the FinFETs through simulation. KONG [16] proposed a variable-latency L1 data cache architecture to reduce the effects of process variations and improve the yield of near-threshold cache.…”

“…(1) To address this problem, previous studies provide the valuable reference knowledge in different fields. Since process variations have been an important issue in the fabrication of modern ICs, they have been studied in various aspects [12][13][14][15][16]. For example, Paul [12] studied the effects of process variations on different types of field-effect transistors (FETs).…”

“…Yoon [15] investigated the performance of sub-5-nm node fin FETs (FinFETs) and nanosheet FETs (NSFETs) in the presence of process variations. KONG [16] studied how process variations influence the near-threshold cache memories.…”

“…The above great works [12][13][14][15][16][17][18][19][20][21][22][23][24] inspired this research to propose a novel investigation method for the S 21 detection circuit.…”