Reduction of power dissipation through parallel optimization of test vector and scan register sequences

Kotásek, Zdenĕk; Škarvada, Jaroslav; Strnadel, Josef

doi:10.1109/ddecs.2010.5491750

Cited by 6 publications

(1 citation statement)

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“…During our previous research activities, we have dealt with the issues related to testability of digital circuits [20], [21], [13]. Besides, we have developed testability analysis method called TASTE [22], [23] for the data path analysis of systems described at the structural level, e.g., register-transfer level (RTL) etc.…”

Section: Our Research Hyphotesis and Motivationmentioning

confidence: 99%

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Rumplik

Strnadel

2011

2011 14th Euromicro Conference on Digital System Design

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Major drawback of high level design methodologies such as RTL can be seen in the following facts. First, they lack of sufficiently precise fault models -compared to sophisticated models available for low level description levels such as logic gate level. Second, since the structure of a design changes significantly with every logic synthesis run, testability analysis is typically performed only after final logic synthesis. As a consequence, results of the analysis could be obtained when it is very costly to reflect them in the high level design. The drawbacks can be removed in several ways. In the contribution, it is supposed the analysis is performed at RTL and is efficient enough to be run after each change in RTL design -giving a designer an immediate information about the change impact to testability parameters. Under the assumption, low computational complexity and accuracy are the requirements posed to the analysis. The latter requirement is met if strong correlation is detected between RTL testability analysis results and lowlevel test pattern generation results. In the paper, it is shown such a correlation exists although relatively simple academic RTL testability analysis solution is compared to widely used commercial gate-level test pattern generation solution. Detail results achieved during the experiments over scan circuits are presented, discussed and summarized in the paper.

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Section: Our Research Hyphotesis and Motivationmentioning

confidence: 99%