Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Kim, M.S.; Roh, Yong-Wan; Park, C.S.; Cho, I.S.; Jeoun, I.H.; Ahn, Eungjin; Kim, K.J.; Nam, Sang Ki; Park, H.S.; Nam, D.W.; Baek, Changhoon; Park, W.H.; Kim, B.H.; Park, S.W.

doi:10.1016/j.surfcoat.2008.06.046

Cited by 3 publications

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“…Simulation of surface topography evolution due to etch and deposition processes and the stresses thereon due to the thermal processes involved in the wafer fabrication processes is an important area of research in the semiconductor industry [93][94][95].…”

Section: Tsv Electrical Characterizationmentioning

confidence: 99%

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Development and characterization of deep reactive ion etching technology for through silicon interconnection

Nagarajan¹

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Deep reactive ion etching (DRIE) is an enabling technology for three dimensional (3D) integration of planar integrated circuits. This work focuses on various challenges associated with deep reactive ion etching technology for realizing through silicon interconnection for 3D Microsystems application. In the first part of the thesis, stress simulation studies were done on TSV structures of various via geometries and shapes to determine the regions of high stress due to CTE mismatch. It was determined that the top and bottom of the vias and the surrounding materials experience maximum mechanical stress. It was also found that the stress is concentrated in the sharp peaks and valleys of the scallops formed by Bosch etch process. A test vehicle was designed and fabricated by copper damascene process with various geometries and barrier structures to experimentally study the effect of sidewall scallops on electrical leakage between adjacent TSV structures. It was shown that the leakage current can be reduced by about nearly 3 orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall for the initial few microns of the depth of the via by using a non-Bosch etch process. This study has shown that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, for vertical TSV etch application by tailoring a short first etch step with smooth sidewall. In the second part of the research, tapered TSV etching technology was developed and characterized for TSV with diameters of 20-100 µm and depth of 100-300 µm for advanced 3D-Packaging application. In this study, the evolution of tapered via etch topography was modeled for various via diameters and experimentally validated within 5-ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library Development and characterization of deep reactive ion etching technology for through silicon interconnection v 10% deviation. It was also experimentally shown that by combining Bosch, RIE and Isotropic etch processes into a multi-step etch process it is possible to achieve acceptable tapered profile of 83-87º and depth from 200-300µm. It was finally demonstrated that a void-free TSV can be formed with good electrical isolation and electrical continuity. In the third part of the work the influence of deep silicon via profile and sidewall roughness on the electrical conduction through the TSV dielectric was studied. Based on extensive experimental characterization it was shown that the sidewall scallops due to Bosch process and curvature defects due to RIE process strongly influences the dielectric conduction in TSV. It was also shown that the scallops and curvature defects causes defectinduced PF type of leakage mechanism between TSVs. It was further shown that smoothening the sidewall defects at top results in significant reduction in leakage current by 3-5 order of magnitude. In conclusion, this research work addressed the critical TSV etch challenges and ...

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Section: Tsv Electrical Characterizationmentioning

confidence: 99%

“…This section describes some of the critical statements. Detailed descriptions of all the statements can be found in Athena User's Manual [94]. have an isotropic angular distribution.…”

Section: Etch Statementsmentioning

confidence: 99%

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Nagarajan¹

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Reliability Improvement by 0.153UM CMOS Using HDP-CVD at STI Edge Sin Liner

Wei-yang¹,

Qin²,

Sun³

et al. 2020

2020 China Semiconductor Technology International Conference (CSTIC)

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Side and Corner Region Non-Uniformities in Grown SiO₂ and Their Implications on Current, Capacitance and Breakdown Characteristics

Bastos,

O'Sullivan,

Higashi

et al. 2024

2024 IEEE International Reliability Physics Symposium (IRPS)

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Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Cited by 3 publications

References 3 publications

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Reliability Improvement by 0.153UM CMOS Using HDP-CVD at STI Edge Sin Liner

Side and Corner Region Non-Uniformities in Grown SiO₂ and Their Implications on Current, Capacitance and Breakdown Characteristics

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Reduction of oxide leakage currents of EEPROM at STI corners using sacrificial oxide/liner SiN/LPCVD MTO

Cited by 3 publications

References 3 publications

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Development and characterization of deep reactive ion etching technology for through silicon interconnection

Reliability Improvement by 0.153UM CMOS Using HDP-CVD at STI Edge Sin Liner

Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics

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Side and Corner Region Non-Uniformities in Grown SiO₂ and Their Implications on Current, Capacitance and Breakdown Characteristics