Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

Lacruz, Jesus O.; García-Herrero, Francisco; Valls, Javier

doi:10.1109/tvlsi.2014.2377194

Cited by 18 publications

(45 citation statements)

References 14 publications

(25 reference statements)

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“…To overcome the drawbacks of T-EMS and T-MM, the proposal in [53] introduces a technique of message compression that reduces the wiring congestion between CN and VN and the storage elements used in the derived architectures. The messages at the output of the CN are reduced to four elementary sets which include the intrinsic and extrinsic information, the path coordinates and the hard-decision symbols.…”

Section: Discussionmentioning

confidence: 99%

“…In this paper we take as starting point the solution from [53] to propose a novel algorithm which reduces the messages that include the intrinsic information and the path coordinates from (q − 1) values to only L messages each one, being L < n m q. This improvement allows us to pass from the number of messages exchanged in [53] to only (q − 1) + 3 × L + d c , saving area in the decoder thanks to the reduction of the memory requirements.…”

Section: Discussionmentioning

confidence: 99%

“…This reduction is offered at the cost of some error-correction degradation and the need of including real-multipliers at the VN for the message approximation. The work from [53] exchanges a fixed number of sets and the size of each set depends of q and d c without introducing any performance loss compared to [42]. Finally, we propose in this work a cardinality reduction of the set ∆Q(a) to only two elements, reducing the total among of bits exchanged to the VN compared to the others proposals from Table 6.2 as can be seen in the example from its rightmost column for the high-rate NB-LDPC code over GF (32).…”

Section: Proposalmentioning

confidence: 99%

“…The original idea comes from [53], where we proposed a method to compress the messages between CN and VN for NB-LDPC message-passing decoders. As the messages are not modified, this method does not introduce any performance loss.…”

mentioning

confidence: 99%

“…As the messages are not modified, this method does not introduce any performance loss. In [54] we particularize the proposal in [53] to T-MM algorithm, and we detail a hardware 95 architecture for the CN processor and for a decoder with layered schedule. In this paper we extend the work in [54], and present a modification of the T-MM algorithm that allow us to reduce even more the number of exchanged messages.…”

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confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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This thesis studies the design of low-complexity soft-decision Non-Binary LowDensity Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps).In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended MinSum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput.Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm 2 . The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million iii NAND gates) is increased in almost five times compared to other proposals from literature.The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF (64) ResumenEn esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps).En la primera parte de la tesis los principales aspectos concernientes a los códi-gos NB-LDPC s...

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: Proposalmentioning

confidence: 99%

mentioning

confidence: 99%

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VLSI algorithms and architectures for non-binary-LDPC decoding

Lacruz¹,

Jesús²

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Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

2019

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An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

Chu

Lee

et al. 2019

IEEE Access

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This paper presents a modified Trellis Min-Max (T-MM) algorithm together with the associated architecture for non-binary (NB) low-density parity-check (LDPC) decoders. The proposed T-MM algorithm is able to reduce the memory requirements for the check-node messages through an efficient compression method and enhance the error-rate performance using the appropriate decompression. A method of updating the a posteriori log-likelihood ratio in the delta domain is used to simplify the computational and storage complexity. In order to enhance the decoding throughput, a low-complexity early termination (ET) scheme is devised by using the hard decisions of the variable-to-check messages, where, although a minor overhead is introduced, there is no visible degradation in error rate. As a proof of concept, a row-parallel layered decoder for the 32-ary (837, 726) LDPC code is implemented using a 90-nm CMOS process. The proposed decoder achieves a throughput of 1.64 Gb/s at 526.32 MHz based on eight iterations and has an area of 6.86 mm 2. When the ET scheme is enabled, the decoder achieves a maximum throughput of 4.68 Gb/s with a frame error rate of 3.25 × 10 −6 at E b /N 0 = 4.5 dB. The proposed NB-LDPC decoder achieves the highest throughput and hardware efficiency compared to the state-of-the-art decoders, even when the ET scheme is not enabled. INDEX TERMS Non-binary low-density parity-check (NB-LDPC) codes, trellis min-max (T-MM) algorithm, layered decoding, early termination (ET), high-throughput decoder, very large scale integration (VLSI) architecture. YEONG-LUH UENG (M'05-SM'15) received the Ph.D. degree in communication engineering from

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Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages

Cited by 18 publications

References 14 publications

VLSI algorithms and architectures for non-binary-LDPC decoding

VLSI algorithms and architectures for non-binary-LDPC decoding

Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes

An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

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