Reduction in PN Junction Leakage for Ni-silicided Small Si Islands by Using Thermal Conduction Heating with Stacked Hot Plates

Itokawa, Hiroshi; Akutsu, Haruko; Nomachi, Akiko; Oono, Hiroshi; Iinuma, T.; Suguro, K.

doi:10.7567/ssdm.2006.e-6-1

Cited by 3 publications

(5 citation statements)

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“…The "pattern effect" of the cold wall RTA system can be significantly avoided by using the hot wall RTA system. [20,21] ECS Transactions, 72 (4) 131-144 (2016) Figure 9 shows the comparative study on NiSi formation anneal on various aspect ratio patterns using the cold wall RTA and hot wall RTA systems. [20,21] The wafers annealed in the cold wall RTA system showed strong line width dependence of sheet resistance while the wafers annealed in the hot wall RTA system showed almost constant sheet resistance down to the line width of 100 nm.…”

Section: E Pattern Density Dependencementioning

confidence: 99%

“…[20,21] ECS Transactions, 72 (4) 131-144 (2016) Figure 9 shows the comparative study on NiSi formation anneal on various aspect ratio patterns using the cold wall RTA and hot wall RTA systems. [20,21] The wafers annealed in the cold wall RTA system showed strong line width dependence of sheet resistance while the wafers annealed in the hot wall RTA system showed almost constant sheet resistance down to the line width of 100 nm. The junction leakage density of n + /p junction, as a function of isolation, also showed strong dependence in wafers annealed in the cold wall RTA system.…”

Section: E Pattern Density Dependencementioning

confidence: 99%

“…(a) Line width dependence of normalized sheet resistance after NiSi formation and (b) junction leakage density of n + /p junction after NiSi formation as a function of isolation width. (c) Schematic illustration of pattern effect in cold wall RTA (radiation heating from tungsten halogen lamps) [21].…”

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confidence: 99%

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(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Yoo¹

2016

ECS Trans.

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Local temperature non-uniformity during rapid thermal annealing (RTA) is an important contributor to within-die process variations which cause significant problems for advanced complimentary metal-oxide-semiconductor (CMOS) device manufacturing. RTA-induced variations strongly depend on circuit layout patterns and optical properties of exposed materials on the surface of the Si wafers. To reduce the “pattern effect”, a hot wall (furnace-based) RTA approach has been proposed and compared with a conventional cold wall (lamp-based) RTA approach in device manufacturing. Nickel and cobalt silicide formations on implanted single crystalline Si in the source/drain region, and implanted poly-Si word lines of memory devices were studied over wide ranges of RTA temperature and time using a hot wall RTA system, which uses mainly natural convection and conduction through ambient gas. Differences between cold wall (radiant) and hot wall (non-radiant) heating on the silicide formation and dopant profiles are compared. The hot wall RTA resulted in superior process uniformity and repeatability regardless of pattern size and emissivity differences on device wafers. Local metal film thickness variations and its interaction with local temperature non-uniformity during RTA are identified as major contributors for the silicidation process variations such as non-uniformity and non-repeatability.

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Section: E Pattern Density Dependencementioning

confidence: 99%

Section: E Pattern Density Dependencementioning

confidence: 99%

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(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Yoo¹

2016

ECS Trans.

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“…Nicket silicide (NiSi) and nickel germanosilicide (NiSiGe) have become preferred materials in CMOS technology for source and drain contacts and NiSi is being considered as a metal gate material as well [1][2][3][4]. With strain engineering demanding different types of strain for NMOS and PMOS transistors [5], Ni metal reacts with substrates that have a wide variety of properties (i.e., chemical composition, doping level, different crystalline phases).…”

Section: Introductionmentioning

confidence: 99%

Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices

Malik¹,

Ouaknine²,

Fukada³

et al. 2007

ECS Trans.

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NiSi has become the preferred material in CMOS technology for source and drain contacts and is being considered as a metal gate material as well. With strain engineering demanding different types of strain for NMOS and PMOS transistors, Ni metal reacts with substrates that have a wide variety of properties (i.e. chemical composition, doping level, different crystalline phases). All of the relevant material combinations need to be taken into account when designing and optimizing an IC manufacturing process. The first part of this study was performed on 300 mm diameter blanket wafers and focuses on Ni metal reactions with lightly doped single-crystal Si and Si0.8Ge0.2. The former is typically used for sources and drains for NMOS transistors (need tensile stress in the channel for electron mobility enhancement), the latter for PMOS transistors (need compressive stress in the channel for hole mobility enhancement). The phase transformation curves for Ni/Si and Ni/Si0.8Ge0.2 are used for identifying the IC process window. In the second part of this study, we used 300 mm diameter device wafers (K8 microprocessor, 65 nm design rule) and targeted four distinct annealing conditions that were chosen based on the blanket wafer experiments.

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“…Thermal processing in an isothermal RTP chamber, significantly reduced pn junction leakage compared to the lamp-based RTP, which undergoes significant diffraction, resulting in non-uniform heating and loss of critical dimension control. [9] The effect of device feature (pattern) size and density on die-level local heating in lamp-based (radiation-based) RTP process was discussed. Theoretical analysis of results was compared with experimental results.…”

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confidence: 99%

Diffraction Originated Local Heating of Nanometer Scale Device Patterns in Lamp-Based Rapid Thermal Annealing

Yoo,

Kang

2007

Meet. Abstr.

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Reduction in PN Junction Leakage for Ni-silicided Small Si Islands by Using Thermal Conduction Heating with Stacked Hot Plates

Cited by 3 publications

References 0 publications

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

(Invited) Pattern and Emissivity Insensitive Dopant Activation and Silicide Contact Formation Annealing in a Hot Wall Rapid Thermal Annealing System

Nickel Silicide and Nickel Germanosilicide Processing in a Near-Isothermal Cavity: Sheet Resistance Curves for Blanket Ni/Si and Ni/SiGe Substrates and Electrical Data for CMOS Devices

Diffraction Originated Local Heating of Nanometer Scale Device Patterns in Lamp-Based Rapid Thermal Annealing

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