Reducing the frequency of tag compares for low power I-cache design

Panwar, Ramesh; Rennels, D. A.

doi:10.1145/224081.224092

Cited by 58 publications

(36 citation statements)

References 6 publications

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“…In the past, many researchers have proposed techniques exploiting a small L0-cache between an MPU core and an L1-cache, e.g., Block Buffering 4),5) , Loop Cache 6) , Filter Cache 7) , and S-Cache 8) . Figure 1 shows a memory subsystem of the conventional L0-cache based approach.…”

Section: Related Workmentioning

confidence: 99%

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion

Yamaguchi

Ishitobi

Ishihara

et al. 2009

IPSJ Transactions on System LSI Design Methodology

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A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for effectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 45% on an average without any performance degradation compared to the conventional L0-cache based approach.

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Section: Related Workmentioning

confidence: 99%

Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion

Yamaguchi

Ishitobi

Ishihara

et al. 2009

IPSJ Transactions on System LSI Design Methodology

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“…The power consumed by instruction memory, when the computation is performed by a processor, can also benefit from synergic approaches that join specialized memory architectures with program optimization. An interesting technique for instruction memory power optimization was proposed by Panwar and Rennels [1995], and later improved by Bellas et al [1998]. This technique aims at improving the effectiveness of instruction buffers.…”

Section: System-level Power Optimizationmentioning

confidence: 99%

System-level power optimization: techniques and tools

Benini¹,

Micheli

Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)

131

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This tutorial surveys design methods for energy-efficient system-level design. We consider electronic systems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods for reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation.This survey is organized around three main phases of a system design: conceptualization and modeling, design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software.

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“…Instruction caches have very regular access patterns and are only accessed via the program counter, and hence are amenable to software-invisible micro-architectural techniques to remove tag checks [16,18,19].…”

Section: Direct Addressingmentioning

confidence: 99%