With the growing concern of process variability, parameterized circuit models are becoming increasingly important for circuit design and veri cation. Although techniques exist to extract compact VCO phase macromodels, a direct parametrization of VCO macromodels over a large set of parametric variations not only results in highly complex models, but also leads to signi cantly high computational cost. In this paper, an ef cient parameterized VCO phase model generation technique is presented to capture the impacts of statistical parametric variations. The model extraction cost of our approach is signi cantly reduced by exploiting circuit-speci c parameter dimension reduction, which effectively reduces the parameter space dimension over which the phase model needs to be extracted. The application of parameter reduction is facilitated by a novel and fast time-domain sampling technique that provides the essential statistical correlation data. Our numerical experiments have shown that the proposed model generation approach is more ef cient than brute-force parametric modeling while producing accurate parameterized phase models that can capture large range parametric variations.