Reducing test time for 3D-ICs by improved utilization of test elevators

Muthyala, Sreenivaas S.; Touba, N.A.

doi:10.1109/vlsi-soc.2014.7004157

2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC) 2014

DOI: 10.1109/vlsi-soc.2014.7004157

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Reducing test time for 3D-ICs by improved utilization of test elevators

Sreenivaas S. Muthyala

N.A. Touba

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2015

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Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Muthyala

Touba

2015

VLSI-SoC: Internet of Things Foundations

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International audienceThree Dimensional Integrated Circuits are an important new paradigm in which different dies are stacked atop one another, and interconnected by Through Silicon Vias (TSVs). Testing 3D-ICs poses additional challenges because of the need to transfer data to the non-bottom layers and the limited number of TSVs available in the 3D-ICs for the data transfer. A novel test compression technique is proposed that introduces the ability to share tester data across layers using daisy-chained decompressors. This improves the encoding of test patterns substantially, thereby reducing the amount of test data required to be stored on the external tester. In addition, an inter-layer serialization technique is proposed, which further reduces the number of TSVs required, using simple hardware to serialize and deserialize the test data. Experimental results are presented demonstrating the efficiency of the technique proposed

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Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Muthyala

Touba

2015

VLSI-SoC: Internet of Things Foundations

View full text Add to dashboard Cite

show abstract

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Reducing test time for 3D-ICs by improved utilization of test elevators

Cited by 1 publication

References 17 publications

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

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